Design of an adaptive flow control algorithm for ATM networks

International audienceThis paper presents several techniques of traffic management such as credit-based and rate-based approaches. An example of these techniques is the simple Leaky Bucket, which is a congestion preventive method, that can easily be implemented. The Adaptive Leaky Bucket algorithm introduces a feed-back mechanism, compared to the common Leaky Bucket, in order to be more flexible and efficient. We focus our study on this algorithm in order to implement it, using a VHDL-based methodology. The design flow starts from an architectural description in RTL level in order to interact easily with current commercial hardware synthesis tools. After simulation and synthesis steps, implementation can be achieved using an ASIC or Xilinx FPGAs

Design of an adaptive flow control architecture for high speed networks (ATM)

International audienceMany flow control and resources management algorithms for ATM networks are chosen by the ATM-Forum. But their complexities make the integration in specific circuits expensive and risky. In this paper we present an architecture allowing flow control and resource management in order to prevent network congestion. The developed idea is to design an adaptive flow control algorithm based on two kinds of cells (data and control) ensuring a continuous dialogue between the transmitter and the receiver. Memory resource management uses the linked list allowing optimal use of memories in a circular way. The system design is achieved using a methodology based on VHDL as a hardware description language. The different steps from specification until circuit layout, have been achieved with a 0.6 µm CMOS technology