37 research outputs found
Time-Space Constrained Codes for Phase-Change Memories
Phase-change memory (PCM) is a promising non-volatile solid-state memory
technology. A PCM cell stores data by using its amorphous and crystalline
states. The cell changes between these two states using high temperature.
However, since the cells are sensitive to high temperature, it is important,
when programming cells, to balance the heat both in time and space.
In this paper, we study the time-space constraint for PCM, which was
originally proposed by Jiang et al. A code is called an
\emph{-constrained code} if for any consecutive
rewrites and for any segment of contiguous cells, the total rewrite
cost of the cells over those rewrites is at most . Here,
the cells are binary and the rewrite cost is defined to be the Hamming distance
between the current and next memory states. First, we show a general upper
bound on the achievable rate of these codes which extends the results of Jiang
et al. Then, we generalize their construction for -constrained codes and show another construction for -constrained codes. Finally, we show that these two
constructions can be used to construct codes for all values of ,
, and
Survey on the Overwintering of Syrphids in Changbai Mountains and Experiments on Artificial Protection of the Overwintering Syrphid Flies
Originating text in Chinese.Citation: Gao, Junfeng, Zhang, Guangxin, Qin, Yongchun, Yu, Kai, Li, Minghai, Qin, Yi. (1993). Survey on the Overwintering of Syrphids in Changbai Mountains and Experiments on Artificial Protection of the Overwintering Syrphid Flies. Chinese Journal of Biological Control, 9(3), 142-144
Self-Ensemble Protection: Training Checkpoints Are Good Data Protectors
As data become increasingly vital for deep learning, a company would be very
cautious about releasing data, because the competitors could use the released
data to train high-performance models, thereby posing a tremendous threat to
the company's commercial competence. To prevent training good models on the
data, imperceptible perturbations could be added to it. Since such
perturbations aim at hurting the entire training process, they should reflect
the vulnerability of DNN training, rather than that of a single model. Based on
this new idea, we seek adversarial examples that are always unrecognized (never
correctly classified) in training. In this paper, we uncover them by modeling
checkpoints' gradients, forming the proposed self-ensemble protection (SEP),
which is very effective because (1) learning on examples ignored during normal
training tends to yield DNNs ignoring normal examples; (2) checkpoints'
cross-model gradients are close to orthogonal, meaning that they are as diverse
as DNNs with different architectures in conventional ensemble. That is, our
amazing performance of ensemble only requires the computation of training one
model. By extensive experiments with 9 baselines on 3 datasets and 5
architectures, SEP is verified to be a new state-of-the-art, e.g., our small
perturbations reduce the accuracy of a CIFAR-10 ResNet18
from 94.56\% to 14.68\%, compared to 41.35\% by the best-known method.Code is
available at https://github.com/Sizhe-Chen/SEP
Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks
In cloud and edge computing models, it is important that compute devices at
the edge be as power efficient as possible. Long short-term memory (LSTM)
neural networks have been widely used for natural language processing, time
series prediction and many other sequential data tasks. Thus, for these
applications there is increasing need for low-power accelerators for LSTM model
inference at the edge. In order to reduce power dissipation due to data
transfers within inference devices, there has been significant interest in
accelerating vector-matrix multiplication (VMM) operations using non-volatile
memory (NVM) weight arrays. In NVM array-based hardware, reduced bit-widths
also significantly increases the power efficiency. In this paper, we focus on
the application of quantization-aware training algorithm to LSTM models, and
the benefits these models bring in terms of resilience against both
quantization error and analog device noise. We have shown that only 4-bit NVM
weights and 4-bit ADC/DACs are needed to produce equivalent LSTM network
performance as floating-point baseline. Reasonable levels of ADC quantization
noise and weight noise can be naturally tolerated within our NVMbased quantized
LSTM network. Benchmark analysis of our proposed LSTM accelerator for inference
has shown at least 2.4x better computing efficiency and 40x higher area
efficiency than traditional digital approaches (GPU, FPGA, and ASIC). Some
other novel approaches based on NVM promise to deliver higher computing
efficiency (up to 4.7x) but require larger arrays with potential higher error
rates.Comment: Published in: 2019 IEEE International Conference on Rebooting
Computing (ICRC