Phonon engineering of atomic-scale defects in superconducting quantum circuits

Noise within solid-state systems at low temperatures, where many of the degrees of freedom of the host material are frozen out, can typically be traced back to material defects that support low-energy excitations. These defects can take a wide variety of microscopic forms, and for amorphous materials are broadly described using generic models such as the tunneling two-level systems (TLS) model. Although the details of TLS, and their impact on the low-temperature behavior of materials have been studied since the 1970s, these states have recently taken on further relevance in the field of quantum computing, where the limits to the coherence of superconducting microwave quantum circuits are dominated by TLS. Efforts to mitigate the impact of TLS have thus far focused on circuit design, material selection, and material surface treatment. In this work, we take a new approach that seeks to directly modify the properties of TLS through nanoscale-engineering. This is achieved by periodically structuring the host material, forming an acoustic bandgap that suppresses all microwave-frequency phonons in a GHz-wide frequency band around the operating frequency of a transmon qubit superconducting quantum circuit. For embedded TLS that are strongly coupled to the electric qubit, we measure a pronounced increase in relaxation time by two orders of magnitude when the TLS transition frequency lies within the acoustic bandgap, with the longest $T_1$ time exceeding $5$ milliseconds. Our work paves the way for in-depth investigation and coherent control of TLS, which is essential for deepening our understanding of noise in amorphous materials and advancing solid-state quantum devices.Comment: 11 + 25 pages, 4 + 22 figures, 6 tables; comments welcome

Building a fault-tolerant quantum computer using concatenated cat codes

We present a comprehensive architectural analysis for a fault-tolerant quantum computer based on cat codes concatenated with outer quantum error-correcting codes. For the physical hardware, we propose a system of acoustic resonators coupled to superconducting circuits with a two-dimensional layout. Using estimated near-term physical parameters for electro-acoustic systems, we perform a detailed error analysis of measurements and gates, including CNOT and Toffoli gates. Having built a realistic noise model, we numerically simulate quantum error correction when the outer code is either a repetition code or a thin rectangular surface code. Our next step toward universal fault-tolerant quantum computation is a protocol for fault-tolerant Toffoli magic state preparation that significantly improves upon the fidelity of physical Toffoli gates at very low qubit cost. To achieve even lower overheads, we devise a new magic-state distillation protocol for Toffoli states. Combining these results together, we obtain realistic full-resource estimates of the physical error rates and overheads needed to run useful fault-tolerant quantum algorithms. We find that with around 1,000 superconducting circuit components, one could construct a fault-tolerant quantum computer that can run circuits which are intractable for classical supercomputers. Hardware with 32,000 superconducting circuit components, in turn, could simulate the Hubbard model in a regime beyond the reach of classical computing

Building a Fault-Tolerant Quantum Computer Using Concatenated Cat Codes

We present a comprehensive architectural analysis for a proposed fault-tolerant quantum computer based on cat codes concatenated with outer quantum error-correcting codes. For the physical hardware, we propose a system of acoustic resonators coupled to superconducting circuits with a two-dimensional layout. Using estimated physical parameters for the hardware, we perform a detailed error analysis of measurements and gates, including cnot and Toffoli gates. Having built a realistic noise model, we numerically simulate quantum error correction when the outer code is either a repetition code or a thin rectangular surface code. Our next step toward universal fault-tolerant quantum computation is a protocol for fault-tolerant Toffoli magic state preparation that significantly improves upon the fidelity of physical Toffoli gates at very low qubit cost. To achieve even lower overheads, we devise a new magic state distillation protocol for Toffoli states. Combining these results together, we obtain realistic full-resource estimates of the physical error rates and overheads needed to run useful fault-tolerant quantum algorithms. We find that with around 1000 superconducting circuit components, one could construct a fault-tolerant quantum computer that can run circuits, which are currently intractable for classical computers. Hardware with 18 000 superconducting circuit components, in turn, could simulate the Hubbard model in a regime beyond the reach of classical computing

Exponential suppression of bit or phase flip errors with repetitive error correction

Realizing the potential of quantum computing will require achieving sufficiently low logical error rates. Many applications call for error rates in the $10^{-15}$ regime, but state-of-the-art quantum platforms typically have physical error rates near $10^{-3}$. Quantum error correction (QEC) promises to bridge this divide by distributing quantum logical information across many physical qubits so that errors can be detected and corrected. Logical errors are then exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold. QEC also requires that the errors are local and that performance is maintained over many rounds of error correction, two major outstanding experimental challenges. Here, we implement 1D repetition codes embedded in a 2D grid of superconducting qubits which demonstrate exponential suppression of bit or phase-flip errors, reducing logical error per round by more than $100\times$ when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analyzing error correlations with high precision, and characterize the locality of errors in a device performing QEC for the first time. Finally, we perform error detection using a small 2D surface code logical qubit on the same device, and show that the results from both 1D and 2D codes agree with numerical simulations using a simple depolarizing error model. These findings demonstrate that superconducting qubits are on a viable path towards fault tolerant quantum computing

Exponential suppression of bit or phase errors with cyclic error correction

Realizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10-15 (refs. 2-9), but state-of-the-art quantum platforms typically have physical error rates near 10-3 (refs. 10-14). Quantum error correction15-17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits