Etude et modélisation du comportement électrique des transistors MOS fortement submicroniques

Membres du jury : Pr Jean-Louis Balladore (ULP), Pr Christian C. Enz (EPFL), Pr Pierre Gentil (INPG), Pr Daniel Mathiot (ULP), Pr Christophe Lallement (ULP), Dr Jean-Michel Sallese (EPFL).Accurate MOS transistor modeling for circuit design and simulation is a constant challenge due to the continuously evolving of CMOS technology. The objective of this thesis is on the one hand to study the main effects resulting from MOSFET miniaturization and on the other hand to propose simple and original analytical models accounting for them. The physical basis necessary to the formulation of an ideal MOSFET model is presented in chapter 2. In addition, a state of the art of the most widely used compact MOSFET models (models for circuit simulation) is also discussed. Chapter 3 is devoted to a detailed study of the extrinsic capacitive behavior of deep-submicron MOSFETs. A new model of parasitic capacitances is developed and then validated by two-dimensional numerical simulations. Chapter 4 introduces a depth study of the quantization effects in both accumulation and inversion layers of n-MOS transistors. The impact of quantum effects on the various electrical characteristics (I-V, C-V) is discussed. A new fully analytical surface-potential-based MOSFET model accounting for the quantum effects is then derived in full detail. This model is valid from accumulation to inversion and does not need any fitting parameter. Within the context of a charge sheet model, it leads to an accurate and continuous description of major MOSFET electrical characteristics such as charges, capacitances, drain current, transconductance, etc. The new model is finally validated by comparison with experimental results from various advanced CMOS technologies. In conclusion, this thesis demonstrates that a pragmatic approach of compact modeling enables the development of simple, efficient and physically coherent models.La modélisation précise des transistors MOS pour la conception et la simulation de circuits est un défi constant en raison de la nature évolutive de la technologie CMOS. L'objectif de cette thèse est d'une part d'étudier les principaux effets résultant de la miniaturisation des TMOS et d'autre part de proposer des modèles analytiques simples et originaux permettant de les prendre en compte. Les bases physiques nécessaires à la formulation d'un modèle idéal sont présentées au chapitre 2, de même qu'un état de l'art des principaux modèles compacts de TMOS (modèles destinés à la simulation de circuits) actuellement utilisés. Le troisième chapitre est consacré à une étude détaillée du comportement capacitif extrinsèque du TMOS fortement submicronique. Un nouveau modèle de capacités parasites est également proposé puis validé à partir de simulations numériques à deux dimensions. Le quatrième chapitre fait état d'une étude approfondie des effets quantiques au sein des transistors n-MOS. L'influence des effets quantiques sur les différentes caractéristiques électriques (I-V, C-V) du TMOS est discutée. Un nouveau modèle quantique, formulé intégralement en potentiel de surface, est alors développé. Ce modèle est complètement analytique, valable de l'accumulation à l'inversion, et ne nécessite aucun paramètre d'ajustement. Utilisé conjointement à un modèle en feuille de charge, il autorise une description précise et continue des caractéristiques électriques majeures du TMOS telles que les charges, les capacités, le courant de drain, la transconductance, etc. Le nouveau modèle est finalement validé par comparaison avec des résultats expérimentaux de différentes technologies CMOS avancées. En conclusion, cette thèse démontre qu'une approche pragmatique de la modélisation compacte permet de réaliser des modèles simples, efficaces et physiquement cohérents

Compact Modeling of MOSFET in VHDL-AMS

In this chapter, we present the capabilities of the VHDL-AMS hardware description language for developing compact models. After a brief description of the VHDL-AMS language, we present two meaningful case studies on design oriented models of MOSFET. The first study focuses on the EKV v2.6 MOSFET model and takes into account the thermo-electrical interaction and the extrinsic aspects. The EKV v2.6 model uses linearization with respect to surface potential, resulting in physically well-based expressions for the whole model. The second study is a simplified version of the MM11 Philips model that takes into account the quantum mechanical effects. MM11 is a compact MOSFET model based on the formulation of the surface potential

Quantum surface potential model suitable for advanced MOSFETs simulation

Abstract-An analytical solution physically accounting for the quantum mechanical effects within the context of an explicit surface-potential-based MOSFET model is presented. The quantum model does not need any additional parameter, and is fully dependent on all terminal voltages. It gives an accurate and continuous description of the surface potential and its derivatives in all regions of operation. The validity of our new modeling approach is confirmed by both comparisons with simulation data (obtained using self-consistent Schrödinger-Poisson numerical calculations) and experimental data from an advanced deepsubmicron CMOS technology

CNTFET modeling and reconfigurable logic circuit design

International audienceThis paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic