The COMQUAD Component Container Architecture and Contract Negotiation

Component-based applications require runtime support to be able to guarantee non-functional properties. This report proposes an architecture for a real-time-capable, component-based runtime environment, which allows to separate non-functional and functional concerns in component-based software development. The architecture is presented with particular focus on three key issues: the conceptual architecture, an approach including implementation issues for splitting the runtime environment into a real-time-capable and a real-time-incapable part, and details of contract negotiation. The latter includes selecting component implementations for instantiantion based on their non-functional properties

Enhanced Hippocampal Long-Term Potentiation and Fear Memory in Btbd9 Mutant Mice

Polymorphisms in BTBD9 have recently been associated with higher risk of restless legs syndrome (RLS), a neurological disorder characterized by uncomfortable sensations in the legs at rest that are relieved by movement. The BTBD9 protein contains a BTB/POZ domain and a BACK domain, but its function is unknown. To elucidate its function and potential role in the pathophysiology of RLS, we generated a line of mutant Btbd9 mice derived from a commercial gene-trap embryonic stem cell clone. Btbd9 is the mouse homolog of the human BTBD9. Proteins that contain a BTB/POZ domain have been reported to be associated with synaptic transmission and plasticity. We found that Btbd9 is naturally expressed in the hippocampus of our mutant mice, a region critical for learning and memory. As electrophysiological characteristics of CA3-CA1 synapses of the hippocampus are well characterized, we performed electrophysiological recordings in this region. The mutant mice showed normal input-output relationship, a significant impairment in pre-synaptic activity, and an enhanced long-term potentiation. We further performed an analysis of fear memory and found the mutant mice had an enhanced cued and contextual fear memory. To elucidate a possible molecular basis for these enhancements, we analyzed proteins that have been associated with synaptic plasticity. We found an elevated level of dynamin 1, an enzyme associated with endocytosis, in the mutant mice. These results suggest the first identified function of Btbd9 as being involved in regulating synaptic plasticity and memory. Recent studies have suggested that enhanced synaptic plasticity, analogous to what we have observed, in other regions of the brain could enhance sensory perception similar to what is seen in RLS patients. Further analyses of the mutant mice will help shine light on the function of BTBD9 and its role in RLS

Towards pervasive treatment of non-functional properties at design and run-time

Disregarding non-functional properties is an important project risk. They have to be taken into consideration throughout the system’s life cycle. Particularly, they must be considered as early as possible in the design phase. Especially in the area of component-based software development it is also important to be able to separate functional and non-functional requirements. Pervasive treatment of nonfunctional properties allows reusing components in previously uncovered environments. In this paper we present an approach that aims at treating non-functional aspects of a system all the way from design time models to runtime enforcement and Quality of Service (QoS) guarantees. In particular, this includes transformation of nonfunctional property specifications from a human-readable in a machine-readable form, scheduling of component usage, and resource reservation

Towards runtime monitoring in real-time systems

In this paper we present the state of our work on runtime monitoring for real-time systems: a way to observe system behavior online without unpredictably disturbing real-time properties. We discuss generic requirements to achieve these properties wherefrom we deduce our monitoring framework architecture. We describe this architecture in detail and discuss several challenges for our implementation called Ferret. We also explain why common operating system primitives, such as message passing or system calls, should not be used for monitoring in the general case and propose a very low-intrusive alternative. We also propose a way of measuring the intrusiveness caused by monitoring. We applied our technique in different scenarios ranging from simple temporal debugging, resource requirement estimation, gaining behavioral information of peripheral hardware devices to build timing models for providing real-time capable service on top of them, up to whole-system views, such as the interaction between concurrently running system threads. Our research platform also contains a para-virtualized version of Linux that we use to run legacy applications. We discuss how to apply our framework to these components with real-time requirements being only one of several important aspects. We also show how to compare the behavior of our para-virtualized Linux kernel with the behavior of the native variant. In this work, we demonstrate how to gain a continuous whole-system view by using only Ferret sensors in all layers of our system, starting from the underlying microkernel, basic microkernel programs, real-time applications, and the para-virtualized Linux kernel, as well as Linux user-space applications.

ASF: AMD64 Extension for Lock-free Data Structures and Transactional Memory

Abstract—Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically executes speculative accesses in the region. Five new instructions are added to demarcate the region, use speculative accesses selectively, and control the speculative hardware context. Programmers can use speculative regions to build flexible multi-word atomic primitives with no additional software support by relying on the minimum guarantee of available ASF hardware resources for lock-free programming. Transactional programs with high-level TM language constructs can either be compiled directly to the ASF code or be linked to software TM systems that use ASF to accelerate transactional execution. In this paper we develop an out-of-order hardware design to implement ASF on a future AMD processor and evaluate it with an in-house simulator. The experimental results show that the combined use of the L1 cache and the LS unit is very helpful for the performance robustness of ASF-based lockfree data structures, and that the selective use of speculative accesses enables transactional programs to scale with limited ASF hardware resources. Keywords-transactional memory, lock-free programming, x86 architecture I