Finite-element simulations of coupling capacitances in capacitively coupled pixel detectors

Capacitively coupled hybrid silicon pixel-detector assemblies are under study for the vertex detector at the proposed future CLIC linear electron-positron collider. The assemblies consist of active CCPDv3 sensors, with 25 μm pixel pitch implemented in a 180 nm High- Voltage CMOS process, which are glued to the CLICpix readout ASIC, with the same pixel pitch and processed in a commercial 65 nm CMOS technology. The signal created in the silicon bulk of the active sensors passes a two-stage amplifier, in each pixel, and gets transferred as a voltage pulse to metal pads facing the readout chip (ROC). The coupling of the signal to the metal pads on the ROC side proceeds through the capacitors formed between the two chips by a thin layer of epoxy glue. The coupling strength and the amount of unwanted cross coupling to neighbouring pixels depends critically on the uniformity of the glue layer, its thickness and on the alignment precision during the flip-chip assembly process. Finite-element calculations of the coupling capacitances were performed, based on a detailed 3-dimensional implementation of the geometrical layout for various alignment parameters. We present the simulation setup and results of coupling and cross-coupling ca- pacitance extractions for the current chip versions (CCPDv3 and CLICpix), as well as results for new chips with optimised designs (C3PD and CLICpix2)

Capacitively Coupled Pixel Detectors: From Design Simulations to Test Beam

Capacitively Coupled Pixel Detectors (CCPDs) are now possible due to new HV-CMOS sensors, where the high voltage (necessary to deplete the sensor) can be applied on CMOS circuits, allowing the sensor to be capacitively coupled to a read out ASIC, avoiding the expensive bump-bonds. An extensive characterisation work, in the ATLAS ITk Upgrade framework, is done in this new sensor technology. TCAD simulations of the pixel designs and TCT measurements on real devices are shown. In addition, automatised wafer probing measurements and the flip-chip, of the sensors with the read-out chips, will be presented. To conclude, test beam measurements done at CERN SPS and at Fermilab, using the UniGE FE-I4 Telescope will be shown and discussed

Caracterização do TimePix3 e de sensores resistentes à radiação para upgrade do VELO

The LHCb experiment located at CERN, Switzerland, studied the difference between matter and antimatter, successfully acquiring data since 2009. The experiment will undergo an upgrade on its detectors to allow operation with higher luminosity, increasing the data acquired by about 10 times. In this thesis, prototypes for the new detectors were studied for the vertex detector (VELO) detector upgrade. Different types of sensors were tested and characterized to determine whether they satisfy the requirements of the upgrade. The, relatively new, TimePix3 readout chip, which is a prototype for future VELO read-out chip, called VELOPix, was used for the tests of the sensors. The analysis of the most important characteristics of TimePix3, relative to VELOPix, and the tests of the sensors are presented. Also, a comparison between different methods of calibration is performed for the proposed TimePix3. The results obtained in this thesis shows that some of the prototypes meet successfully the critical requirements (radiation resistance and tolerance to high voltage) of the upgrade

New pixel-detector technologies for the ATLAS ITk upgrade and the CLIC vertex detector

This thesis contains the Ph.D. work done on the characterization of novel silicon pixel detectors, based on the new HV-CMOS technology, for the ATLAS ITk upgrade and the future CLIC vertex detector. In order to provide the best precision and accuracies for the respective ATLAS and CLIC physics measurement plans, both ATLAS ITk and the CLIC vertex detectors are designed with high demanding requirements, pushing to the limits the standard technologies used for silicon pixel detectors. Current silicon pixel detectors are built using a standard planar silicon sensor coupled to a read-out chip via bump-bonds, demanding the design of two different devices and the coupling process between them, called hybridization. The new HV-CMOS technology allows implementing a sensor and read-out device in the same silicon substrate, combining the high-voltage capabilities of planar silicon sensors with the signal amplification and digitization of dedicated read-out chips, eliminating the need of the detector hybridization. The current ATLAS vertex and tracker detectors will be replaced by an all-silicon detector, covering a total area of a few hundred square meters, meaning the need of many detector modules to be designed, produced and assembled. In addition, with the higher irradiation levels to come with the High Luminosity LHC upgrade, the detector needs to have a higher radiation-hardness, while keeping the same performance of the current detector. The CLIC vertex detector, on the other hand, does not have a problem with radiation tolerance due to the nature of its electron-positron collisions. Nevertheless, to achieve the high precision physics measurements targeted, the detector module needs to be very thin (< 100 $\mu$m) and designed with small pixel sizes (25 $\mu$m), which current detector hybridization technologies are not fully capable to provide with the necessary production yield. HV-CMOS monolithic prototypes have been investigated for implementation at the outer pixel layers of the ATLAS ITk detector, helping with the detector design and production time. For the CLIC vertex detector, HV-CMOS devices are investigated for implementation as capacitively coupled pixel detector (CCPD) modules, where the hybridization between the sensor and read-out devices is done via a thin layer of a dielectric glue, instead of the expensive and complex bump-bonds. In addition, the capacitive coupling of the sensor to the read-out allows having pixel sizes smaller than what currently bump-bonding techniques can provide, contributing to the miniaturization of the pixel size and, therefore, increasing the achievable detector pointing resolution. The usage of the HV-CMOS technology is first analyzed with Finite Element simulations regarding the coupling between the sensor and read-out electronics (for CCPD prototypes), continuing with the process of detector assembly into modules and, finally, the detector module performance is tested using dedicated particle beams tests in different test-beam facilities. The UniGE FE-I4 particle telescope, necessary for the tracking of the particle beam as it goes through the prototypes, was used and improved regarding the automatization of performance measurement scans and support for different electrical and mechanical requirements of different prototypes. The capacitive coupling process was optimized using a semi-automated flip-chip machine. A planarity in the order of a few hundred μrad was achieved, with an alignment accuracy < 2 $\mu$m between the two devices. The cross-talk among multiple coupled pixel-pairs was simulated and found to be < 4% for the prototype investigated for the CLIC vertex, while an ATLAS CCPD prototype simulation, with a pixel pitch 2x larger than the CLIC prototype, resulted in a cross- coupling < 0.5%. The HV-CMOS prototypes investigated on test-been has shown good performance before and after irradiation. The fully monolithic HV-CMOS ATLAS prototype has shown a detection efficiency of 99.7% measured before irradiation, when tested with a high voltage reversed bias of 60 V and low signal threshold of about 750 electrons. After irradiation up to a dose of 10$^{15}$n$_{eq}$/cm$^{2}$, the efficiency has decreased slightly to 99.2%, with 90 V high-voltage bias and a detection threshold equivalent to 1 ̃000 electrons. The results from the different HV-CMOS detector prototypes, concerning production and performance, has indicated that the HV-CMOS technology is suitable for its application in future high-energy particle collision experiments, such as the outer layers of the ATLAS ITk upgrade as well as for the future CLIC vertex detector

A silicon pixel detector prototype for the CLIC vertex detector

A silicon pixel detector prototype for CLIC, currently under study for the innermost detector surrounding the collision point. The detector is made of a High-Voltage CMOS sensor (top) and a CLICpix2 readout chip (bottom) that are glued to each other. Both parts have a size of 3.3 x 4.0 $mm^2$ and consist of an array of 128 x 128 pixels of 25 x 25 \micro m^2 size

The CLICTD monolithic silicon pixel-detector with sub-pixel segmentation

A CLICTD silicon-pixel detector test chip, designed for the requirements of the CLIC tracking detector. The chip has a footprint of 5x5 $mm^2$ and is produced as a monolithic CMOS detector, comprising both the sensor and the readout electronics. It contains a sensitive area segmented in 2048 readout channels. Each readout channel has a dimension of 30 x 300 \micro m^2 and is divided into 8 sub-pixels of 37.5 x 30 \micro m^2 size. For testing, the prototype is connected to a printed circuit board using small aluminium wire-bonds. The CLIC tracking detector will contain roughly 140 $m^2$ of silicon pixel detectors. The sub-pixel segmentation scheme tested with the CLICTD chip will help to reduce the number of readout channels for this large instrumented area, while maintaining a high measurement precision

Allpix2^2: A Modular Simulation Framework for Silicon Detectors

Allpix$^2$ (read: Allpix Squared) is a generic, open-source software framework for the simulation of silicon pixel detectors. Its goal is to ease the implementation of detailed simulations for both single detectors and more complex setups such as beam telescopes from incident radiation to the digitised detector response. Predefined detector types can be automatically constructed from simple model files describing the detector parameters. The simulation chain is arranged with the help of intuitive configuration files and an extensible system of modules, which implement separate simulation steps such as realistic charge carrier deposition with the Geant4 toolkit or propagation of charge carriers in silicon using a drift-diffusion model. Detailed electric field maps imported from TCAD simulations can be used to precisely model the drift behaviour of charge carriers within the silicon, bringing a new level of realism to Monte Carlo based simulations of particle detectors. This paper provides an overview of the framework and a selection of different simulation modules, and presents a comparison of simulation results with test beam data recorded with hybrid pixel detectors. Emphasis is placed on the performance of the framework itself, using a first-principles simulation of the detectors without addressing secondary ASIC-specific effects.Allpix 2 (read: Allpix Squared) is a generic, open-source software framework for the simulation of silicon pixel detectors. Its goal is to ease the implementation of detailed simulations for both single detectors and more complex setups such as beam telescopes from incident radiation to the digitised detector response. Predefined detector types can be automatically constructed from simple model files describing the detector parameters

Development of novel single-die hybridisation processes for small-pitch pixel detectors

Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution – an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%.Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25 µm and 55 µm are presented in this contribution — an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on Anisotropic Conductive Film (ACF). The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25 µm pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50 µm to 130 µm. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house Electroless Nickel Immersion Gold (ENIG) plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55 µm pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques. This contribution introduces the two interconnect processes and presents preliminary hybridisation results with CLICpix2 and Timepix3 sensors and ASICs.Hybrid pixel detectors require a reliable and cost-effective interconnect technology adapted to the pitch and die sizes of the respective applications. During the ASIC and sensor R&D phase, especially for small-scale applications, such interconnect technologies need to be suitable for the assembly of single dies, typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D programme and the AIDAinnova collaboration, innovative hybridisation concepts targeting vertex-detector applications at future colliders are under development. Recent results of two novel interconnect methods for pixel pitches of 25um and 55um are presented in this contribution -- an industrial fine-pitch SnAg solder bump-bonding process adapted to single-die processing using support wafers, as well as a newly developed in-house single-die interconnection process based on ACF. The fine-pitch bump-bonding process is qualified with hybrid assemblies from a recent bonding campaign at Frauenhofer IZM. Individual CLICpix2 ASICs with 25um pixel pitch were bump-bonded to active-edge silicon sensors with thicknesses ranging from 50um to 130um. The device characterisation was conducted in the laboratory as well as during a beam test campaign at the CERN SPS beam-line, demonstrating an interconnect yield of about 99.7%. The ACF interconnect technology replaces the solder bumps by conductive micro-particles embedded in an epoxy film. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACF using a flip-chip device bonder. The required pixel pad topology is achieved with an in-house ENIG plating process. This newly developed ACF hybridisation process is first qualified with the Timepix3 ASICs and sensors with 55um pixel pitch. The technology can be also used for ASIC-PCB/FPC integration, replacing wire bonding or large-pitch solder bumping techniques

Pixel detector hybridization and integration with anisotropic conductive adhesives

International audienceA reliable and cost-effective interconnect technology is required for the development of hybrid pixel detectors. The interconnect technology needs to be adapted for the pitch and die sizes of the respective applications. For small-scale applications and during the ASIC and sensor development phase, interconnect technologies must also be suitable for the assembly of single-dies typically available from Multi-Project-Wafer submissions. Within the CERN EP R&D program and the AIDAinnova collaboration, innovative and scalable hybridization concepts are under development for pixel-detector applications in future colliders. This contribution presents recent results of a newly developed in-house single-die interconnection process based on Anisotropic Conductive Adhesives (ACA). The ACA interconnect technology replaces solder bumps with conductive micro-particles embedded in an epoxy layer applied as either film or paste. The electro-mechanical connection between the sensor and ASIC is achieved via thermocompression of the ACA using a flip-chip device bonder. A specific pixel-pad topology is required to enable the connection via micro-particles and create cavities into which excess epoxy can flow. This pixel-pad topology is achieved with an in-house Electroless Nickel Immersion Gold process that is also under development within the project. The ENIG and ACA processes are qualified with a variety of different ASICs, sensors, and dedicated test structures, with pad diameters ranging from 12 μm to 140 μm and pitches between 20 μm and 1.3 mm. The produced assemblies are characterized electrically, with radioactive-source exposures, and in tests with high-momentum particle beams. A focus is placed on recent optimization of the plating and interconnect processes, resulting in an improved plating uniformity and interconnect yield