A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard

A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard

K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor

In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power from the switch on-resistance will also be decreased, leading to a boosted inductor Q at switch ON-state. The equivalent inductance, quality factor, and self-resonance frequency at switch ON/OFF states are analyzed and derived. For comparison, K-band VCOs have been designed and fabricated in a 130nm BiCMOS process with the Q-boosted and conventional switched inductors. Measured results show that the phase noise has been typically improved by 2–5dB at 100 kHz and 1 MHz offset at switch ON-state, using the Q-boosted switched inductor

A Broadband Power Amplifier in 130-nm SiGe BiCMOS Technology

This letter describes an ultra-broadband power amplifier (PA) in a 130 nm SiGe:C BiCMOS technology. To achieve this broadband while keeping a compact chip size, an on-chip transformer-based dual-LC-tank power matching method is proposed and implemented for achieving this 54.8 % fractional large-signal 3 dB bandwidth (28.5-50 GHz). Additionally, a high quality factor (Q) by-pass MOM capacitor is proposed and implemented in the transistor layout to decrease the parasitic inductance influence for increasing the gain and keep unconditional stability of the PA. The complete PA achieves a measured saturated output power of 19.2 dBm with 21.5 GHz (28.5-50 GHz) large-signal -3 dB bandwidth at 3.3 V power supply. This broadband PA is only 0.63 mm, and the measured S21 is higher than 22.5 dB from 18.5 to 50 GHz with recorded 70.3 % fractional small-signal 3 dB bandwidth for silicon-based cascode PA. The measured peak OP1dB is 16.8 dBm at 44 GHz, and the maximum power-added efficiency (PAE) is 23.9 % at 32 GHz

A Compact 10–14.5 GHz Quadrature Hybrid with Digitally Reconfigurable I/Q Phase in SiGe BiCMOS Process

In this article, the development of a compact 10–14.5 GHz quadrature hybrid with digitally reconfigurable I/Q phase in 130 nm SiGe BiCMOS process is presented. Thanks to the switched capacitance loaded on I/Q path of the quadrature hybrid, the I/Q phase difference can be optimized and digitally reconfigured. The equivalent model is analyzed with even/odd mode theory, and the ABCD matrix is used for the circuit derivation. In order to obtain high coupling coefficient, the broadside coupled line sections are utilized, and compact hybrid size can be realized accordingly. Measured results show that the compact quadrature hybrid has optimized phase difference of 90 ± 1.0° and amplitude difference less than ±0.5 dB for 10–14.5 GHz, with an ultra-compact size of 460 µm × 151 µm, or 0.031λ0 × 0.011λ0. Meanwhile, with the seven reconfigurable phase states, the quadrature hybrid I/Q phase can be digitally reconfigured for a range of 3 degrees to compensate the I/Q phase imbalance in the quadrature system, without DC power consumption

A K-Band FMCW Frequency Synthesizer Using Q-Boosted Switched Inductor VCO in SiGe BiCMOS for 77 GHz Radar Applications

In this article, a fractional-N phase-locked loop (PLL) with integrated chirp generation circuit block for a 76~81 GHz frequency-modulated continuous-wave (FMCW) radar system is presented. Thanks to the switched inductor voltage-controlled oscillator (VCO) topology, the linearity, phase noise, chirp bandwidth, and chirp rate of the FMCW synthesizer can be optimized for the short-range radar (SRR) and long-range radar (LRR) applications, with switch at ON/OFF states, respectively, according to different requirements and concerns. In this way, the proposed FMCW synthesizer shows improved phase noise for switch OFF-state, good for LRR applications, compared to the conventional single-varactor VCOs or cap-bank VCOs. The switch loss at ON-state is further decreased with the Q-boosting technique, which helps the FMCW synthesizer to simultaneously obtain a wide chirp bandwidth, steep modulation rates and good phase noise for SRR applications. The FMCW synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 1.7 × 1.9 mm2, and consumes 330 mW from a 3.3 V voltage supply. Measured results show that the FMCW synthesizer can cover 25.3~27 GHz (with a frequency tripler to fully cover 76~81 GHz band), showing optimized phase noise, chirp bandwidth, linearity, and modulation rates performance. The measured K-band phase noise is −110.5 dBc/Hz for switch OFF-state, and −106 dBc/Hz for switch ON-state at 1 MHz offset. The normalized root mean square (RMS) frequency error is 518 kHz for chirp rate of ±14.6 MHz/μs and 1.44 MHz for chirp rate of ±39 MHz/μs for the 77 GHz band. Moreover, the integrated waveform generator offers fully programmability in chirp rate, duration and bandwidth, which supports multi-slope chirp generations. With a frequency tripler, the chip is well suited for the 76~81 GHz FMCW radar system

An E-Band SiGe High Efficiency, High Harmonic Suppression Amplifier Multiplier Chain With Wide Temperature Operating Range

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA 1,2 ), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between -40 °C and 125 °C with the proposed temperature compensation bias circuits

A 150-GHz Transmitter with 12-dBm Peak Output Power Using 130-nm SiGe:C BiCMOS Process

This article presents a compact 150-GHz transmitter with 12-dBm Psat and 17-dB conversion gain. This D-band transmitter is composed of a frequency doubler, a micromixer, a two-stage gm-boosting power amplifier (PA), and an on-chip dielectric resonate (DR) antenna. At sub-terahertz, the output power and the gain are the limiting factors for the transmitter's performance. In this work, gm-boosting topology is implemented to achieve the 17-dB gain by taking advantage of the base inductor without sacrificing the PA's stability. The output power of the 150-GHz PA is enhanced by the proposed phase compensation method. In this proposed method, an auxiliary inductor is added for adjusting the phase difference to decrease the introduced loss from power combining and matching networks. The imbalance at the LO port is also reduced by the proposed capacitor and the resistor compensation method. From 140 to 160 GHz, the transmitter delivers more than 8-dBm output power, with the maximum Psat of 12 dBm at 148 GHz. This transmitter exhibits a conversion gain of 17 dB and an output 1-dB compression point (OP1dB) of 11.4 dBm. The transmitter exhibits the highest output power, the highest OPdB, competitive conversion gain, and bandwidth among any silicon-based transmitters in D-band, to the best of our knowledge

A -28.5 dB EVM 64-QAM 45 GHz Transceiver for IEEE 802.11aj

This article presents a fully integrated IEEE 802.11aj direct-conversion transceiver system in a 120-nm SiGe:C BiCMOS technology. The system includes a transmitter, a receiver, and two onboard substrates integrated waveguide-fed Yagi-Uda antennas. In the millimeter-wave frequency band, the common-mode (CM) signal in a transformer-based balun is a limiting factor for the linearity of differential devices. In this work, we analyze the cause of the CM effect and provide fast impedance equalization with a passive component compensation method to resolve this problem, which improves the linearity of the transmitter. A T-type second-order harmonic termination method is applied at the power amplifier (PA) output to further improve the linearity of the transmitter. The self-mixing method-based power detector is adopted at the output of the transmitter to have an accurate image signal and local oscillator (LO) leakage calibration. The transmitter reaches an output 1-dB compression point (OP1,dB) of 14.6-16.4 dBm and a conversion gain (CG) higher than 24 dB in the IEEE 802.11aj frequency band, operating from 42.3 to 48.4 GHz. The receiver achieves a 3.8-4.1-dB noise figure, -18.7- to -22-dBm input 1-dB compression point, and a CG better than 43.8 dB in the IEEE 802.11aj frequency band. In the system wireless data transmission test, the transceiver is fully compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode, and the measured transmitter-to-receiver EVM is better than -28.5 dB at a 1-m distance over the IEEE 802.11aj frequency band. Compared to other states of the art, the transmitter's OP1,dB is the highest, and the demonstrated transceiver system delivers the highest performance in the IEEE 802.11aj wireless link