A gate-delay model for high-speed CMOS circuits

Abstract-- As signal speeds increase and gate delays decrease for high-performance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gateoutput impedances make it more difficult to empirically characterize gate-delay models. Moreover, the single-input-switching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today’s high-speed logic paths. In this paper a new empirical gate delay model is proposed. Instead of building the empirical equations in terms of capacitance loading and input-signal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived k-factor models and switch-resistor models to efficiently: 1) handle capacitance shielding due to metal interconnect resistance, 2) model the RC interconnect delay, and 3) provide tighter bounds for simultaneous switching. I

Method and apparatus for simulating a microelectric interconnect circuit

A method and apparatus for simulating a microelectronic circuit or system includes the storing of a microelectronic circuit or system representation in a computer and then transforming the representation into an equivalent DC circuit containing resistive, capacitive and inductive elements. Then, a directed graph of the DC equivalent circuit is generated and a spanning tree is constructed therefrom. The spanning tree is then actually or virtually traversed to obtain multiple generations of circuit moments. The moments are then used to calculate the poles and residues for a given node and generate an approximate model of the circuit's transient response at that node. Moment shifting is used to provide for a stable approximate model. The actual residues corresponding to the coefficients of the time domain representation for the model can be calculated using the first q-1 moments. This constitutes a partial-Pade approximation.Board of Regents, University of Texas Syste