Estimation of body weight and body surface area in swamp buffaloes using visual image analysis

The three dimensional computerized visual image analysis was performed to evaluate the body weight (BW) and body surface area (BSA) in swamp buffaloes. Nineteen swamp buffaloes were measured the conformation by linear measurement compared to 3D body scanner at different points : body height (A), heart girth (B), shoulder width (C), iliac width (D), ischial tuberosity width (E), the length between shoulder and ileal wing (F, G), the length between ileal wing to ischial tuberosity (H, I) and the length between shoulder to ischial tuberosity (J1, J2).  The significant correlation was found between these two methods.  The 3D body scanner was then performed in 28 males and 39 females for BW and 68 males and 74 non-pregnant and 31 pregnant females for BSA estimation. The appropriate models to estimate BW in buffaloes were BW = - 1174.07 + 4.31 (B) + 7.75 (FG) (R2 = 0.76, P<0.001), BW (male) = -1265.99 + 4.94(B) + 14.41(D)  (R2 = 0.81; P<0.001) and BW (female) = -563.66 + 7.94 (C ) + 14.77 (E)  (R2 = 0.86; P<0.001).  For BSA, the appropriate equations were BSA = -4.31 + 0.034(A) + 0.036(J1J2) (R2 = 0.82, P<0.001), BSA (male) = -4.01 + 0.032(A) + 0.037(J1J2) (R2 = 0.816, P<0.001) and BSA (female) = -3.50 + 0.013(A) + 0.012(B) + 0.040(E) + 0.015(J1J2) (R2 = 0.916, P<0.001). In conclusion, the 3D body scanner can be used to estimate BW and BSA in buffaloes with different models among males and females

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Following a review of previous work in this area, a presentation is made which illustrates the impact of a naive application of DVS in a system incorporating a time-triggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) and then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use of a form of 'sandwich delay' to reduce the impact of changes to the scheduler overhead which arise as a result of frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency. The impact of these algorithms on both jitter and energy consumption is illustrated empirically on a representative hardware platform, using both 'dummy' task sets and a more realistic case study. In designs for which low jitter is an important consideration, at least a limited degree of task pre-emption may be required. A simple time-triggered hybrid (TTH) scheduler can be used to achieve such behaviour. A novel TTH secluding algorithm (TTH-jDVS) is presented and evaluated, again through use of dummy task sets and a case study. The third piece of experimental work presented in this thesis illustrates that --- in situations where minimal jitter is required --- hardware support is required. To illustrate the potential of such an approach a final case study is employed