Engineering of III-Nitride Semiconductors on Low Temperature Co-fired Ceramics

This work presents results in the feld of advanced substrate solutions in order to achieve high crystalline quality group-III nitrides based heterostructures for high frequency and power devices or for sensor applications. With that objective, Low Temperature Co-fred Ceramics has been used, as a noncrystalline substrate. Structures like these have never been developed before, and for economic reasons will represent a groundbreaking material in these felds of Electronic. In this sense, the report presents the characterization through various techniques of three series of specimens where GaN was deposited on this ceramic composite, using diferent bufer layers, and a singular metal-organic chemical vapor deposition related technique for low temperature deposition. Other single crystalline ceramic-based templates were also utilized as substrate materials, for comparison purposes

Characterization of Buffer Layers for SiC CVD

Silicon Carbide has been grown by rapid thermal carbonization of (100) and (111) Si surfaces at atmospheric pressure using 1 lpm hydrogen (H2) as a carrier gas and propane (C3H8) with concentrations ranging from 0.025-1 5%. RHEED investigations have shown single crystalline SiC as well as additional phases depending on the propane concentration. A set of kinetic phase diagrams were determined. The chemical nature was examined by AES. At concentrations below 0,1% additional silicon and an increasing number of defects were found. The growth on (100) substrates has shown a change in orientation toward (111). Above 0.6% a carbon rich polycrystalline layer covering completely the surface was formed. The carbon has both graphitic and carbidic nature. The graphitic content could be decreased by post deposition H2 annealing without changing the polycrystalline nature of this top layer. Best crystallinity were found at 1250°C, 0.15% propane and 30-90 S

Gate-tunable hysteresis response of field effect transistor based on sulfurized Mo

Hysteresis effects and their tuning with electric fields and light were studied in thin film molybdenum disulfide transistors fabricated from sulfurized molybdenum films. The influence of the back-gate voltage bias, voltage sweep range, illumination, and AlOx encapsulation on the hysteresis effect of the back-gated field effect transistors was studied and quantified. This study revealed the distinctive contribution of MoS2 surface, MoS2/SiO2 interface defects and their associated traps as primary sources of of hysteresis