4 research outputs found

    Antiferroelectric negative capacitance from a structural phase transition in zirconia

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    Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO2_2 and ZrO2_2) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO2_2 gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically 'forbidden' region of the antiferroelectric transition in ZrO2_2 and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions

    ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS

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    Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring improvements to the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor improvements by stacking multiple smaller 2D dies vertically instead of using a single large 2D die. The objective of this research is to explore and exploit novel design configurations possible with 3D ICs. Furthermore, tool flows and algorithms were developed to augment and capitalize on the commercially available 2D Electronic Design Automation (EDA) tools to support our exploration. While most of the work is done based on assumptions related to the state-of-the-art research fabrication methods for 3D such as Monolithic 3D ICs, we also develop new flows to refine the 3D IC routing with commercially available fabrication techniques such as hybrid bonding and micro-bump based 3D ICs.Ph.D

    High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors

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    Monolithic 3-D IC (M3-D) is a promising solution to improve the performance and energy-efficiency of modern processors. But, designers are faced with challenges in design tools and methodologies, especially for power and thermal verifications. We developed a new physical design flow that optimally places and routes cache modules in one tier and logic gates in the other. Our tool also builds high-quality clock and power delivery networks targeting logic-on-memory M3-D designs. Finally, we developed a sign-off analysis tool flow to evaluate power, performance, area (PPA), thermal, and voltage-drop quality for given M3-D designs. Using our complete register transfer level (RTL)-to-Graphic Design System (GDS) tool flow, we designed commercial quality 2-D and M3-D implementation of Arm Cortex-A7 and Cortex-A53 processors in a commercial 28-nm technology. Experimental results show that our 3-D processors offer 20% (A7) and 21% (A53) performance gain, compared with their 2-D commercial counterparts. The voltage-drop degradation of our 3-D Cortex-A7 and Cortex-A53 processors is less than 3% of the supply voltage, while temperature increase is 10.71 °C and 13.04 °C, respectively.SCOPUS: ar.jinfo:eu-repo/semantics/publishe
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