Nanostructured Indium Tin Oxides and Other Transparent Conducting Oxides: Characteristics and Applications in the THz Frequency Range

Transparent conductors are essential for optoelectronic components operating in the far-infrared or terahertz (THz) frequency range. Indium tin oxide (ITO), extensively used in the visible, is semi-transparent in the far-infrared frequency range. Other types of bulk transparent conducting oxides (TCOs), such as aluminum-doped zinc oxide (AZO) and aluminum and ytterbium-doped zinc oxide (AYZO), have not yet been explored for THz applications. Recently, biomimic nanomaterials have been shown to exhibit exotic optical properties, e.g., broadband, omnidirectional antireflective properties. Indeed, nanostructured ITO was found to exhibit the above desirable characteristics. In this chapter, we describe the fabrication and characterization of several TCOs, including ITO nanomaterials and several types of bulk TCO thin films, e.g., AZO and AYZO. Performance of THz phase shifters with ITO nanomaterials as transparent electrodes and liquid crystals for functionalities is presented

Deep Geometry Handling and Fragment-wise Molecular 3D Graph Generation

Most earlier 3D structure-based molecular generation approaches follow an atom-wise paradigm, incrementally adding atoms to a partially built molecular fragment within protein pockets. These methods, while effective in designing tightly bound ligands, often overlook other essential properties such as synthesizability. The fragment-wise generation paradigm offers a promising solution. However, a common challenge across both atom-wise and fragment-wise methods lies in their limited ability to co-design plausible chemical and geometrical structures, resulting in distorted conformations. In response to this challenge, we introduce the Deep Geometry Handling protocol, a more abstract design that extends the design focus beyond the model architecture. Through a comprehensive review of existing geometry-related models and their protocols, we propose a novel hybrid strategy, culminating in the development of FragGen - a geometry-reliable, fragment-wise molecular generation method. FragGen marks a significant leap forward in the quality of generated geometry and the synthesis accessibility of molecules. The efficacy of FragGen is further validated by its successful application in designing type II kinase inhibitors at the nanomolar level

DOI: 10.1561/1000000003 FPGA Design Automation: A Survey

Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA technology over the past two decades. The purpose of this paper is to meet the demand for an up-todate comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5–10 years. The paper focuses on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow which includes: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. We hope that this paper can be used both as a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field

Logic and layout optimizaton for sequential circuits

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps: high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further broken into a few optimization problems. In this thesis we study several such problems in logic and layout synthesis.We study how the technique of retiming can be introduced to enhance the solution of three problems in logic synthesis. Specifically, we consider a partial scan approach to the problem of design-for-testability in which a set of scan signals (instead of scan flip-flops) is pre-selected. We propose an algorithm that uses retiming to position flip-flops on the pre-selected scan signals so that these signals can be scanned. Next, we combine resynthesis with retiming to reduce the cycle time of a sequential circuit. We also integrate retiming into the technology mapping step for look-up table based field programmable gate arrays (FPGAs). We present an optimal cycle time technology mapping algorithm for sequential circuits.In layout synthesis, we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). We propose two area minimization algorithms for general floorplans. Both algorithms can be viewed as generalizations of the classical area minimization algorithm by Otten and Stockmeyer. A fast pseudo-polynomial area minimization algorithm for an important class of hierarchical floorplans is also proposed. We settle an open problem on the complexity of the area minimization problem for hierarchical floorplans by showing it to be NP-complete. Finally, we study a graph constraint reduction problem in symbolic layout compaction. We present a polynomial algorithm that achieves optimal reduction.U of I OnlyETDs are only available to UIUC Users without author permissio

Partial Scan with Preselected Scan Signals

Abstract { A partial scan approach proposed recently selects scan signals without considering the availability of the ip-ops (FFs). Such a n approach can greatly reduce the number of scan signals since maximum freedom is allowed in scan signal selection. To actually scan the selected signals, we, however, must make them FF-driving signals. In this paper, we study the problem of modifying and retiming a circuit to make a pre-selected set of scan signals FF-driving signals while preserving the set of cycles being broken. We present a new approach for solving this problem. Based on the new approach w e design an ecient algorithm. Unlike a previous algorithm which inherently has no control over the area overhead incurred during the modication, our algorithm explicitly minimizes the area overhead. The algorithm has been implemented and encouraging results were obtained

Optimal clock period FPGA technology mapping for sequential circuits

Abstract � In this paper � we study the technology mapping problem for sequential circuits for LUT� based FPGAs. Existing approaches map the combi� national logic between �ip��ops �FFs � while assum� ing the positions of the FFs are �xed. We study in this paper a new approach to the problem � in which retiming is integrated into the technology mapping process. We present a polynomial time technology mapping algorithm that can produce a mapping so� lution with the minimum clock period while assuming FFs can be arbitrarily repositioned by retiming. The algorithm has been implemented. Experimental re� sults on benchmark circuits clearly demonstrate the advantage of our approach. For many benchmark circuits � our algorithm produced mapping solutions with clock periods not attainable by a mapping al� gorithm based on existing approaches � even when it employs an optimal delay mapping algorithm for combinational circuits.

Enhanced Optically–Excited THz Wave Emission by GaAs Coated with a Rough ITO Thin Film

In this study, we report enhancement of terahertz (THz) radiation with indium-tin-oxide (ITO) thin-film deposited on semi-insulating gallium arsenide substrate (SI-GaAs). The amplitude of THz emission from both ITO/SI-GaAs and bare SI-GaAs substrate as a function of optical pump (i) incident angle, (ii) polarization angle, and (iii) power were investigated. The enhancement of peak amplitude of a THz pulse transmitted through the ITO/SI-GaAs sample in comparison to bare SI-GaAs substrate varied from 100% to 0% when the pump incidence angle changed from 0° to 50°. The maximum enhancement ratio of peak amplitude for a coated sample relative to the bare substrate is approximately up to 2.5 times at the minimum pump intensity of 3.6 TW/m2 and gradually decreased to one at the maximum pump intensity of 20 TW/m2. From outcomes of these studies, together with data on surface and material characterization of the samples, we show that THz emission originates from the ITO/GaAs interfaces. Further, both interface-field-induced transient current and field-induced optical rectification contribute to the observed THz signal. Observed enhancement was tentatively attributed to surface-plasmon-induced local field enhancement, coupled with constructive interference of forward and retro-reflected backward THz emission from the ITO/GaAs interfaces. The polarity-flip reported previously for very thin Au-coated GaAs was not observed. This was explained by the wide-bandgap, transparency and lower free carriers of ITO. For best results, the incident angle should be in the range of 0 to 30° and the incident polarization should be 0 to 45°. We further predict that the ITO thin film of suitable thickness or with engineered nanostructures, post-annealed under optimum conditions may lead to further enhancement of THz radiation from ITO-coated semiconductor surfaces