Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC

A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper

A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Design and testing of CMOS radiation detectors for High Energy Physics Experiments

In recent years, the study and the development of novel architectures and tech- nologies to improve performance of silicon pixel detectors became a pivotal node for High Energy Physics (HEP) experiments. Their extremely tight constraints of spatial resolution, low power dissipation, speed, granularity, signal-to-noise ratio and radiation hardness, led the scientific community to continuously research new solutions to satisfy newer and more stringent requirements. In this context, the two main categories of detectors technologies have been represented by Hybrid Pixel Detectors (HPDs) and Monolithic Active Pixel Sensors (MAPS). Traditionally, HPDs constitute the more widespread technology for particle pixel detectors: due to their excellent characteristics, they are adopted for the inner layers of the most of current main HEP experiments. However, on the other side, the relatively novel monolithic sensors technology became recently more and more interesting as leading replacing technology due to its improved radiation hardness and the lower material budget and cost with respect to HPDs. In this thesis an introduction to these technologies will be carried out and some related research results will be shown. In Chapter 1 Hybrid Pixel Detectors technology will be described, with an additional part dedicated to some literature examples about HEP experiments which adopted this kind of sensors for their inner layers. This chapter acts as an introduction to the CHIPIX65 (CHIp for PIXel detector in a 65 nm process) prototype shown in Chapter 3 and to the Phase-Locked Loop described in Chapter 5.In Chapter 2 MAPS (Monolithic Active Pixel Sensors) technology will be intro- duced, from the early prototypes based on 3-T and 4-T architecture until the last examples of monolithic sensors implemented inside more recent particle detectors upgrades. This part is preparatory to Chapter 5, where the MATISSE prototype is described both to the development and to the testing point of view. Chapter 3 is dedicated to CHIPIX65 project and the development of a novel prototype of an 65 nm CMOS HPD: realized in collaboration of some INFN Italian groups, this is the first example of HPD fully developed in a sub-micron CMOS technology. Starting with a short introduction to architecture and readout modes, this chapter shows some important testing results presented in Strasbourg during an IEEE MIC-NSS Conference talk in 2016. Chapter 4 is fully dedicated to a low-noise and compact Phase-Locked Loop (PLL) built in the same 65 nm CMOS technology. After some theoretical and introductory sections, the prototype will be described and test results provided. Chapter 5 is fully dedicated to the development and test of a prototype of MAPS, called MATISSE (Monolithic AcTIve pixel SenSor Electronics). Developed by INFN groups of Turin and Padua, University of Trento and TIFPA, it is an example of a fully-depleted monolithic active sensor. Here, some sensor and readout electronics will be described, followed by some tests. These results have been presented during a poster session in Atlanta during the IEEE MIC-NSS Conference in 2017. Appendices will cover some follow-up topics related to the previous sections. Appendix A summarizes radiation effects on silicon devices, both total dose and heavy-ions effect: this section is useful to referring to all the parts related to radiation hardness tests of described prototypes. Appendix B outlines some practical guidelines about Process Design Kit (PDK) of a given technology process. Indeed, before starting the design of any ASIC device, a PDK needs to be provided by the foundry, installed and configured in order to allow to work with. Appendix C is dedicated to some theoretical issues on oscillator phase noise, which represent a huge subject in Phase-Lock Loop theory; however, since it is not covered by the analysis and tests on the PLL prototype, it has been chosen to put this part separately to Chapter 4

Upgrade of the ALICE Experiment Letter Of Intent

This Letter of Intent (LoI) presents the plans of the ALICE (A Large Ion Collider Experiment [1]) collaboration to extend its physics programme, in order to fully exploit the scientific potential of the Large Hadron Collider (LHC) for fundamental studies of QCD, with the main emphasis on heavy-ion collisions. The proposed enhancement of the ALICE detector performance will enable detailed and quantitative characterization of the high density, high temperature phase of strongly interacting matter, together with the exploration of new phenomena in QCD. In the following we outline the physics motivation for running the LHC with heavy ions at high luminosities and summarize the performance gains expected with the upgraded ALICE detector. With the proposed timeline of initiating high-rate operation after the 2018 Long Shutdown (LS2), the objectives of our upgrade plans will be achieved by collecting data into the mid-2020's

Upgrade of the ALICE Experiment Letter Of Intent

This Letter of Intent (LoI) presents the plans of the ALICE (A Large Ion Collider Experiment [1]) collaboration to extend its physics programme, in order to fully exploit the scientific potential of the Large Hadron Collider (LHC) for fundamental studies of QCD, with the main emphasis on heavy-ion collisions. The proposed enhancement of the ALICE detector performance will enable detailed and quantitative characterization of the high density, high temperature phase of strongly interacting matter, together with the exploration of new phenomena in QCD. In the following we outline the physics motivation for running the LHC with heavy ions at high luminosities and summarize the performance gains expected with the upgraded ALICE detector. With the proposed timeline of initiating high-rate operation after the 2018 Long Shutdown (LS2), the objectives of our upgrade plans will be achieved by collecting data into the mid-2020’s

A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

Technical design report for the upgrade of the ALICE inner tracking system

ALICE (A Large Ion Collider Experiment) is studying the physics of strongly interacting matter, and in particular the properties of the Quark-Gluon Plasma (QGP), using proton-proton, proton-nucleus and nucleus-nucleus collisions at the CERN LHC (Large Hadron Collider). The ALICE Collaboration is preparing a major upgrade of the experimental apparatus, planned for installation in the second long LHC shutdown in the years 2018-2019. A key element of the ALICE upgrade is the construction of a new, ultra-light, high-resolution Inner Tracking System (ITS) based on monolithic CMOS pixel detectors. The primary focus of the ITS upgrade is on improving the performance for detection of heavy-flavour hadrons, and of thermal photons and low-mass di-electrons emitted by the QGP. With respect to the current detector, the new Inner Tracking System will significantly enhance the determination of the distance of closest approach to the primary vertex, the tracking efficiency at low transverse momenta, and the read-out rate capabilities. This will be obtained by seven concentric detector layers based on a 50 \u3bcm thick CMOS pixel sensor with a pixel pitch of about 30 730 \u3bcm2. This document, submitted to the LHCC (LHC experiments Committee) in September 2013, presents the design goals, a summary of the R&D activities, with focus on the technical implementation of the main detector components, and the projected detector and physics performance