Design of a High-Speed UART VLSI Library Cell

We present the sampling and decoding algorithm and the VLSI implementation of a high-speed UART (Universal Asynchronous ReceiverTransmitter) library cell to be used in custom or semi-custom VLSI chip designs. Our approach to data recovery, which is based on signal preprocessing and an innovative decoding algorithm, operates with as few as 2 samples per bit time, thus achieving a high communication rate. Using a clock of frequency f MHz, this UART can transmit and receive at a rate of up to f Mbits/s, without any internal multiplication of the clock frequency. The current design, that was submitted for fabrication operates at data rates up to 25 Mbits/s (ES2 1.5 µm CMOS standard cell technology), while extensive simulations for a higher performance technology (1 µm gatearray) verify that our cell operates at data rates up to 60 Mbits/s. We are currently performing post-fabrication testing, and some preliminary results show that the prototypes operate succesfully at the data rate of 20 M..

Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI

We present the sampling and decoding algorithm and the VLSI implementation of a high-speed UART (Universal Asynchronous Receiver- Transmitter) library cell to be used in custom or semi-custom VLSI chip designs. Our approach to data recovery, which is based on signal preprocessing and an innovative decoding algorithm, operates with as few as 2 samples per bit time, thus achieving a high communication rate. Using a clock of frequency 'f' MHz, this UART can transmit and receive at a rate of up to 'f' Mbits/s, without any internal multiplication of the clock frequency. The current design, that was submitted for fabrication operates at data rates up to 25 Mbits/s (ES2 1.5 um CMOS standard cell technology), while extensive simulations for a higher performance technology (1 um gate-array) verify that our cell operates at data rates up to 60 Mbits/s. We are currently performing post-fabrication testing, and some preliminary results show that the prototypes operate succesfully at the data rate of 20 MHz. The resulting cell is small and flexible, making it suitable to be used as a building block in chip designs. It can serve as an interface between serial asynchronous communication links, or as a building block for fast and inexpensive networks

Pipelined memory shared buffer for VLSI switches

ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more expensive than the latter. We present a new org anization for a shared buffer with its associated switching and cut-through functions. It is simpler and smaller than wide or interleaved org anizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion. The first word of a packet is transferred to/from the first bank, followed by a ‘‘wave’ ’ of similar operations for the remaining words in the remaining banks. An FPGA-based prototype is operational, while standard-cell and full-custom chips are being submitted for fabrication. Simulation of the full-custom version indicates that, even in a conservative 1-micron CMOS technology, a 64 Kbit central buffer for an 8×8 switch operates at 1 Gbps/link (worst case) and fits in 45 mm 2 including crossbar and cut-through

Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ‘‘ATLAS I’ ’ Single-Chip Switch

ABSTRACT: ATLAS I is a single-chip gigabit ATM switch. Reliable and efficient com-munication with quality-of-service guarantees is essential in real-time systems. ATLAS I routes data cells reliably by implementing credit-based flow control on its IEEE Std. 1355 ‘‘HIC’ ’ links. Quality-of-service and efficiency are supported by imple-menting three levels of priority and by eliminating head-of-line blocking with multi-lane credit flow control. 1

VC-level Flow Control and Shared Buffering in the Telegraphos Switch

ABSTRACT: We present three implementations of a fixed-size-packet switch featuring shared buffering, virtual circuit (VC) flow control, and 3 clock cycle cutthrough latency, for applications in gigabit LAN’s, networks of workstations, multiprocessor networks, and WAN’s. VC-level credit-based flow control is essential in data communications, to offer full throughput utilization while preventing throughput collapse under heavy, bursty, and hot-spot traffic. We describe in detail the implementation of VC flow control-- one of few such implementations in hardware. We present an FPGA-based prototype that was built and is now functional, a standard-cell ASIC CMOS single-chip implementation that is currently under fabrication, and a full-custom layout of the pipelined memory shared buffer, which is also under fabrication inside a test chip. VC flow control costs less than 15 % of the switch area in both the FPGA and the ASIC versions. Full-custom yields 4 times less area and 3 times higher speed for the buffer and crossbar, compared to the semi-custom implementation

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

: We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM's, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special access Cop..

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

ABSTRACT: We describe the queue management block of ATLAS I, a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM’s, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special acces

Implementation of ATLAS I: aSingle-Chip ATM Switch with Backpressure

ABSTRACT: ATLAS I is a single-chip ATM switch with 10 Gb/s throughput, a shared buffer, 3priority levels, multicasting, load monitoring, and optional credit-based flow control. This 6-million-transistor 0.35-micron CMOS chip is about to be taped out for fabrication. We present here the implementation of ATLAS I; we report on the design complexity and silicon cost of the chip and of the individual functions that it supports. Based on these metrics, we evaluate the architecture ofthe switch. The evaluation points in the direction of increasing the cell buffer size and dropping VP/VC translation, while other possible modifications are also discussed. The cost of credit support (10 % in chip area and 4 % in chip power) is minuscule compared to its benefits, i.e. compared to what alternative architectures have to pay in order to achieve comparable performance levels