Digital-to-time converters for spur correction in digital frequency synthesis

The demand for wireless communication, mobile computing and multifunctional portable electronics has driven System-on-Chip (SoC) solutions, where many functional blocks running at difference clock frequencies coexist on the same chip. This requires an on-chip clock source that must be able to generate a wide range of frequencies in a flexible way. The concept of Pulse-Output Digital-to-Frequency Converter (DFC) has been the starting point for the research developed in this thesis. A key limitation of this architecture is deterministic jitter, due to periodic phase errors produced by its digital core. The research described in this thesis focuses on reducing the deterministic jitter exploiting Digital-to-Time Converters (DTCs). The design of a new fully-differential DTC, suitable for GHz operating frequencies, is developed. To characterize the DTC in terms of resolution and linearity, we propose a method to measure its delay steps with unprecedented time resolution, as low as femto-seconds, with common lab equipment. The method exploits digital phase modulation to produce spurs related to the size of the DTC delay-steps. To correct the deterministic jitter of a Pulse-Output DFC, we propose in this thesis a spur correction with the aforementioned developed DTC. The system analysis shows that a 11-bit DTC with a few LSB INL is capable to push down the sub-harmonics spurs of the Pulse-Output DFC to -60 dBc. A mathematical model is derived that (1) predicts the strength of all the sub-harmonic spurs and (2) relates the maximum spur to the DTC Integral Non-Linearity (INL) in a simple, closed-form expression. This allows the designer to derive DTC INL requirements given a Spurious-Free Dynamic Range (SFDR) target. A fully-integrated prototype of a Pulse-Output DFC with DTC-based spur correction has been implemented in 1.2V 65nm CMOS technology. Measured worst case spurs are < -44dBc for an arbitrarily programmable frequency up to 500 MHz, with a power consumption of 51mW. Overall, it is shown that the spur-reduction technique based on DTC correction is promising for flexible digitally programmable frequency synthesis

A sensitive method to measure the integral nonlinearity of a digital-to-time converter based on phase modulation

A digital-to-time converter (DTC) produces a time delay based on a digital code. Similar to data converters, linearity is a key metric for a DTC and it can be characterized by its integral nonlinearity (INL). However, measuring the INL of a subpicosecond-resolution DTC is problematic, even when using the best available high-speed oscilloscopes. In this brief we propose a new method to measure the INL of a DTC by applying digital phase modulation and measuring the output spectrum with a spectrum analyzer. The frequency selectivity of this method allows for an improved measurement resolution down to a few femtoseconds and allows measuring an INL below 100 fs. The proposed method is verified by behavioral simulations and is employed to measure the INL of a high-resolution DTC realized in the 65-nm CMOS, with a time resolution of 25 fs and a standard deviation of 27 fs

Digital-to-Frequency Converters with a DTC: Theoretical Analysis of the Output SFDR

In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave

A high-linearity digital-to-time converter technique: constant-slope charging

A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog converter. Measurements with a 55 MHz crystal clock demonstrate a full-scale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequency-domain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps full-scale delay and 0.34% at 19 ps are measured, representing 8–9 bit effective INL-limited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW