Co-Adjusting Voltage/Frequency State and Interrupt Rate for Improving Energy-Efficiency of Latency-Critical Applications

As the power/energy consumption is one of the major contributors to the Total Cost of Ownership (TCO), improving power/energy efficiency is crucial for large-scale data centers where latency-critical applications are commonly accommodated while computing resources are usually under-utilized. For improving the power/energy efficiency of processors, most of the commercial processors support Dynamic Voltage and Frequency Scaling (DVFS) technology that enables to adjust Voltage and Frequency state (V/F state) of the processor dynamically. In particular, for the latency-critical applications, many prior studies propose power management policies using the DVFS for the latency-critical applications, which minimizes the performance degradation or satisfies the Service Level Objectives (SLOs) constraints. Meanwhile, although the interrupt rate also affects the response latency and energy efficiency of latency-critical applications considerably, those prior studies just introduce policies for V/F state adjustment while not considering the interrupt rate. Therefore, in this article, we investigate the impact of adjusting the interrupt rate on the tail response latency and energy consumption. Through our experimental results, we observe that adjusting interrupt rate along with V/F state management varies the performance and energy consumption considerably, and provides an opportunity to reduce energy further by showing latency overlap between different V/F states. Based on the observation, we show the quantitative potential in improving energy efficiency of co-adjusting V/F state and interrupt rate with a simple management policy, called Co-PI. Co-PI searches the most energy-efficient combination of the V/F state and interrupt rate from the latency and energy tables that we obtain through offline profiling, and reflect the combination to the core and NIC. Co-PI reduces energy consumption by 34.1% and 25.1% compared with performance and ondemand governors while showing the almost same tail response latency with the performance governor that operates cores at the highest V/F state statically. © 1991 BMJ Publishing Group. All rights reserved.1

Copper selenide film electrodes prepared by combined electrochemical/chemical bath depositions with high photo-electrochemical conversion efficiency and stability

Copper selenide (of the type Cu2-xSe) film electrodes, prepared by combined electrochemical (ECD) followed by chemical bath deposition (CBD), may yield high photo-electrochemical (PEC) conversion efficiency (~14.6%) with no further treatment. The new ECD/CBD-copper selenide film electrodes show enhanced PEC characteristics and exhibit high stability under PEC conditions, compared to the ECD or the CBD films deposited separately. The electrodes combine the advantages of both ECD-copper selenide electrodes (in terms of good adherence to FTO surface and high surface uniformity) and CBD-copper selenide electrodes (suitable film thickness). Effect of annealing temperature, on the ECD/CBD film electrode composition and efficiency, is discussed.The results of this work are partly based on K. Murtada M.Sc. Thesis, under direct supervision of H.S. Hilal. Other experimental measurements and calculations, including dark current experiments, film thickness measurement, electrical conductivity, SEM analysis, XRD &AFM analysis revisions were performed by A. Zyoud after the thesis completion. Additional film electrode stability experiments under PEC conditions, were also performed by A. Zyoud after the Thesis completion. SEM micrographs and EDX spectra were measured by T.W. Kim and H-J.C. at the KIER, Korea. The XRD patterns were measured by D-H. Park and H. Kwon at PUK. M.H.S. Helal and H. Bsharat contributed with literature search, discussions and modeling. M. Faroun measured AFM micrographs at Al-Quds University. H.S. Hilal acknowledges financial support from ANU, Islamic Development Bank, Al-Maqdisi Project and Union of Arab Universities. T.W. Kim and H-J. Choi acknowledge financial support from the framework of the Research and Development Program of the Korea Institute of Energy Research (B6-2523)

Low-resistance stretchable electrodes using a thick silver layer and a PDMS-PDMS bonding technique

In this paper, a stretchable silver electrode having high stretching capability and good stability is demonstrated using a poly (dimethyl siloxane) (PDMS) substrate bonding technique. By bonding two silver electrodes (bonding electrode), low initial sheet resistance and good stretching capability under a 38% strain condition were achieved. It was also shown that the bonding electrode has good stability under a 1000-cycle prolonged stress condition (15% strain). The origin of the good stretching capability of the bonding sample is explained as percolation of the current path between the top and bottom electrodes. Using a resistor network model, the percolation of the current path was quantitatively characterized

CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads

In data-center servers, the dynamic core allocation for Latency-Critical (LC) applications can play a crucial role in improving energy efficiency under Service Level Objective (SLO) constraints, allowing cores to enter idle states (i.e., C-states) that consume less power by turning off a part of hardware components of a processor. However, prior studies focus on the core allocation for application threads while not considering cores involved in network packet processing, even though packet processing affects not only response latency but also energy consumption considerably. In this paper, we first investigate the impacts of the explicit core allocation for network packet processing on the tail response latency and energy consumption while running LC applications. We observe that co-adjusting the number of cores for network packet processing along with the number of cores for LC application threads can improve energy efficiency substantially, compared with adjusting the number of cores only for application threads, as prior studies do. In addition, we propose a dynamic core allocation, called CoreNap, which allocates/de-allocates cores for both LC application threads and packet processing. CoreNap measures the CPU-utilization by application threads and packet processing individually, and predicts response latency and power consumption when the combination of core allocation is enforced via a lightweight prediction model. Based on the prediction, CoreNap chooses/enforces the energy-efficient combination of core allocation. Our experimental results show that CoreNap reduces energy consumption by up to 18.6% compared with state-of-the-art study that adjusts cores only for LC application in parallel packet processing environments. IEEEFALS

A Resiliency Coordinator Against Malicious Attacks for Cyber-Physical Systems

Resiliency of cyber-physical systems (CPSs) against malicious attacks has been a topic of active research in the past decade due to widely recognized importance. Resilient CPS is capable of tolerating some attacks, operating at a reduced capacity with core functions maintained, and failing gracefully to avoid any catastrophic consequences. Existing work includes an architecture for hierarchical control systems, which is a subset of CPS with wide applicability, that is tailored for resiliency. Namely, the architecture consists of local, network and supervision layers and features such as simplex structure, resource isolation by hypervisors, redundant sensors/actuators, and software defined network capabilities. Existing work also includes methods of ensuring a level of resiliency at each one of the layers, respectively. However, for a holistic system level resiliency, individual methods at each layers must be coordinated in their deployment because all three layers interact for the operation of CPS. For this purpose, a resiliency coordinator for CPS is proposed in this work. The resiliency coordinator is the interconnection of central resiliency coordinator in the supervision layer, network resiliency coordinator in the network layer, and finally, local resiliency coordinators in multiple physical systems that compose the physical layer. We show, by examples, the operation of the resiliency coordinator and illustrate that RC accomplishes a level of attack resiliency greater than the sum of resiliency at each one of the layers separately. © 2022 ICROS

Impact of Flush+Reload Cache Side-channel Attack on the CPS Environment and Detection Technique of Flush+Reload Cache Side-channel Attack

The security of computer systems is highly critical in CPS (Cyber-Physical Systems) as the use of physical systems controlled by compromised computing systems poses a threat to the users. In this paper, we first describe a security attack that exploits the weaknesses of computer hardware, known as the cache-side channel attack, and discuss the impact of the attack on the CPS environment. Next, we propose a two-stage attack detection technique that can dynamically detect the cache-side attack based on flush+reload by using hardware performance counters while supporting online monitoring. The experimental results demonstrate that our proposed technique can detect the attacker processes effectively with zero failure rates when co-operating with certain applications. © ICROS 2021.1

Altered antioxidant system stimulates dielectric barrier discharge plasma-induced cell death for solid tumor cell treatment.

This study reports the experimental findings and plasma delivery approach developed at the Plasma Bioscience Research Center, Korea for the assessment of antitumor activity of dielectric barrier discharge (DBD) for cancer treatment. Detailed investigation of biological effects occurring after atmospheric pressure non-thermal (APNT) plasma application during in vitro experiments revealed the role of reactive oxygen species (ROS) in modulation of the antioxidant defense system, cellular metabolic activity, and apoptosis induction in cancer cells. To understand basic cellular mechanisms, we investigated the effects of APNT DBD plasma on antioxidant defense against oxidative stress in various malignant cells as well as normal cells. T98G glioblastoma, SNU80 thyroid carcinoma, KB oral carcinoma and a non-malignant HEK293 embryonic human cell lines were treated with APNT DBD plasma and cellular effects due to reactive oxygen species were observed. Plasma significantly decreased the metabolic viability and clonogenicity of T98G, SNU80, KB and HEK293 cell lines. Enhanced ROS in the cells led to death via alteration of total antioxidant activity, and NADP+/NADPH and GSH/GSSG ratios 24 hours (h) post plasma treatment. This effect was confirmed by annexin V-FITC and propidium iodide staining. These consequences suggested that the failure of antioxidant defense machinery, with compromised redox status, might have led to sensitization of the malignant cells. These findings suggest a promising approach for solid tumor therapy by delivering a lethal dose of APNT plasma to tumor cells while sparing normal healthy tissues

NoHammer: Preventing Row Hammer with Last-Level Cache Management

Row Hammer (RH) is a circuit-level phenomenon where repetitive activation of a DRAM row causes bit-flips in adjacent rows. Prior studies that rely on extra refreshes to mitigate RH vulnerability demonstrate that bit-flips can be prevented effectively. However, its implementation is challenging due to the significant performance degradation and energy overhead caused by the additional extra refresh for the RH mitigation. To overcome challenges, some studies propose techniques to mitigate the RH attack without relying on extra refresh. These techniques include delaying the activation of an aggressor row for a certain amount of time or swapping an aggressor row with another row to isolate it from victim rows. Although such techniques do not require extra refreshes to mitigate RH, the activation delaying technique may result in high-performance degradation in false-positive cases, and the swapping technique requires high storage overheads to track swap information. We propose NoHammer, an efficient RH mitigation technique to prevent the bit-flips caused by the RH attack by utilizing Last-Level Cache (LLC) management. NoHammer temporarily extends the associativity of the cache set that is being targeted by utilizing another cache set as the extended set and keeps the cache lines of aggressor rows on the extended set under the eviction-based RH attack. Along with the modification of the LLC replacement policy, NoHammer ensures that the aggressor row's cache lines are not evicted from the LLC under the RH attack. In our evaluation, we demonstrate that NoHammer gives 6% higher performance than a baseline without any RH mitigation technique by replacing excessive cache misses caused by the RH attack with LLC hits through sophisticated LLC management, while requiring 45% less storage than prior proposals. © 2023 IEEE.FALS

Network Packet Processing Mode-Aware Power Management for Data Center Servers

In data center servers, power management (PM) exploiting Dynamic Voltage and Frequency Scaling (DVFS) for processors can play a crucial role to improve energy efficiency. However, we observe that current PM policies (i.e., governors) not only considerably increase tail response time (i.e., violate a given Service Level Objective (SLO)) but also hurt energy efficiency. Tackling limitations of current PM governors, we propose NMAP, Network packet processing Mode-Aware Power management. NMAP improves energy efficiency while satisfying given SLOs, considering packet processing status on a core for PM by monitoring transitions between network packet processing modes - interrupt and polling. Tracking the transitions, NMAP detects moments that a core cannot process packets fast enough and forces the core to immediately raise the voltage and frequency (V/F) state. As a result, NMAP can provide not only low response time but also low energy consumption. Our experiment shows that NMAP improves tail response time by up to 4.1 compared with the ondemand governor, reducing energy by up to 44.6 percent compared with the performance governor.1