151 research outputs found
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Solder Contamination
There are two sources of contamination in solder alloys. The first source is trace elements from the primary metals used in the as-manufactured product, be that product in ingot, wire, or powder form. Their levels in the primary metal are determined by the refining process. While some of these trace elements are naturally occurring materials, additional contamination can result from the refining and/or forming processes. Sources include: furnace pot liners, debris on the cutting edges of shears, rolling mill rollers, etc. The types and levels of contaminants per solder alloy are set by recognized industrial, federal, military, and international specifications. For example, the 63Sn-37Pb solder purchased to the ASTM B 32 standard can have maximum levels of contamination for the following metals: 0.08(wt.)%Cu, 0.001 %Cd, 0.005%Al, 0.25%Bi, 0.03%As, 0.02%Fe, and 0.005 %Zn. A second cause of contamination in solders, and solder baths in particular, is their actual use in soldering operations. Each time a workpiece is introduced into the bath, some dissolution of the joint base metal(s), protective or solderable coatings, and fixture metal takes place which adds to contamination levels in the solder. The potential impurities include Cu; Ni; Au or other noble metals used as protective finishes and Al; Fe; and Zn to name a few. Even dissolution of the pot wall or liner is a source of impurities, typically Fe
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A microstructural analysis of solder joints from the electronic assemblies of dismantled nuclear weapons
MC1814 Interconnection Boxes from dismantled B57 bombs, and MC2839 firing Sets from retired W70-1 warheads were obtained from the Pantex facility. Printed circuit boards were selected from these components for microstructural analysis of their solder joints. The analysis included a qualitative examination of the solder joints and quantitative assessments of (1) the thickness of the intermetallic compound layer that formed between the solder and circuit board Cu features, and (2) the Pb-rich phase particle distribution within the solder joint microstructure. The MC2839 solder joints had very good workmanship qualities. The intermetallic compound layer stoichiometry was determined to be that of Cu6Sn5. The mean intermetallic compound layer thickness for all solder joints was 0.885 mm. The magnitude of these values did not indicate significant growth over the weapon lifetime. The size distribution of the Pb-rich phase particles for each of the joints were represented by the mean of 9.85 {times} 10{sup {minus}6} mm{sup 2}. Assuming a spherical geometry, the mean particle diameter would be 3.54 mm. The joint-to-joint difference of intermetallic compound layer thickness and Pb-rich particle size distribution was not caused by varying thermal environments, but rather, was a result of natural variations in the joint microstructure that probably existed at the time of manufacture. The microstructural evaluation of the through-hole solder joints form the MC2839 and MC1814 components indicated that the environmental conditions to which these electronic units were exposed in the stockpile, were benign regarding solder joint aging. There was an absence of thermal fatigue damage in MC2839 circuit board, through-hole solder joints. The damage to the eyelet solder joints of the MC1814 more likely represented infant mortality failures at or very near the time of manufacture, resulting from a marginal design status of this type of solder joint design
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Capillary flow solder wettability test
A test procedure was developed to assess the capillary flow wettability of solders inside of a confined geometry. The test geometry was comprised of two parallel plates with a controlled gap of constant thickness (0.008 cm, 0.018 cm, 0.025 cm, and 0.038 cm). Capillary flow was assessed by: (1) the meniscus or capillary rise of the solder within the gap, (2) the extent of void formation in the gap, and (3) the time-dependence of the risen solder film. Tests were performed with the lead-free solders
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Intermetallic compound layer growth kinetics in non-lead bearing solders
The introduction of alternative, non-lead bearing solders into electronic assemblies requires a thorough investigation of product manufacturability and reliability. Both of these attributes can be impacted by the excessive growth of intermetallic compound (IMC) layers at the solder/substrate interface. An extensive study has documented the stoichiometry and solid state growth kinetics of IMC layers formed between copper and the lead-free solders: 96.5Sn-3.5Ag (wt.%), 95Sn-5Sb, 100Sn, and 58Bi-42Sn. Aging temperatures were 70--205 C for the Sn-based solders and 55--120 C for the Bi-rich solder. Time periods were 1--400 days for all of the alloys. The Sn/Cu, Sn-Ag/Cu, and Sn-Sb/Cu IMC layers exhibited sub-layers of Cu{sub 6}Sn{sub 5} and Cu{sub 3}Sn; the latter composition was present only following prolonged aging times or higher temperatures. The total layer growth exhibited a time exponent of n = 0.5 at low temperatures and a value of n = 0.42 at higher temperatures in each of the solder/Cu systems. Similar growth kinetics were observed with the low temperature 58Bi-42Sn solder; however, a considerably more complex sub-layer structure was observed. The kinetic data will be discussed with respect to predicting IMC layer growth based upon solder composition
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Ultraminiature resonator accelerometer
A new family of microminiature sensors and clocks is being developed with widespread application potential for missile and weapons applications, as biomedical sensors, as vehicle status monitors, and as high-volume animal identification and health sensors. To satisfy fundamental technology development needs, a micromachined clock and an accelerometer have initially been undertaken as development projects. A thickness-mode quartz resonator housed in a micromachined silicon package is used as the frequency-modulated basic component of the sensor family. Resonator design philosophy follows trapped energy principles and temperature compensation methodology through crystal orientation control, with operation in the 20--100 MHz range, corresponding to quartz wafer thicknesses in the 75--15 micron range. High-volume batch-processing manufacturing is utilized, with package and resonator assembly at the wafer level. Chemical etching of quartz, as well as micromachining of silicon, achieves the surface and volume mechanical features necessary to fashion the resonating element and the mating package. Integration of the associated oscillator and signal analysis circuitry into the silicon package is inherent to the realization of a size reduction requirement. A low temperature In and In/Sn bonding technology allows assembly of the dissimilar quartz and silicon materials, an otherwise challenging task. Unique design features include robust vibration and shock performance, capacitance sensing with micromachined diaphragms, circuit integration, capacitance-to-frequency transduction, and extremely small dimensioning. Accelerometer sensitivities were measured in the 1--3 ppm/g range for the milligram proof-mass structures employed in the prototypes evaluated to date
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Modeling non-isothermal intermetallic layer growth in the 63Sn-37Pb/Cu system
A model describing diffusion-controlled growth of multiple intermetallic layers and the displacement of the interfaces between layers was developed and implemented in a 1-D computer code based on method-of-lines. The code was applied to analysis of intermetallic layer growth in isothermal solder aging experiments performed with 100 Sn/Cu and 63Sn-37Pb/Cu solder-substrate systems. Analyses indicated that intermetallic layer growth was consistent with a bulk diffusion mechanism involving Cu and/or Sn. In this work, nonisothermal solder-aging experiments were done with the 63Sn- 37Pb/Cu system using two temperature histories (4 cycles/day between 223-443 K, and 72 cycles/day between 223-443 K). Isothermal experiments were also done at 443 K. Thickness of Cu{sub 3}Sn and Cu{sub 6}Sn{sub 5} intermetallic layers were determined vs time for each temperature history. An updated version of the model and code were used to predict the intermetallic layer growth. Arrhenius expressions for diffusion coefficients in both Cu3Sn and Cu6Sn5 layers were determined. Agreement between prediction and experiment was generally good. In some cases, predicted layer growth was less than experiment, but within error. This paper describes the nonisothermal experiments and a comparison of predicted and observed layer growth vs time
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Environmentally compatible solder materials for thick film hybrid assemblies
New soldering materials and processes have been developed over the last several years to address a variety of environmental issues. One of the primary efforts by the electronics industry has involved the development of alternative solders to replace the traditional lead-containing alloys. Sandia National Laboratories is developing such alternative solder materials for printed circuit board and hybrid microcircuit (HMC) applications. This paper describes the work associated with low residue, lead-free soldering of thick film HMC`s. The response of the different materials to wetting, aging, and mechanical test conditions was investigated. Hybrid test vehicles were designed and fabricated with a variety of chip capacitors and leadless ceramic chip carriers to conduct thermal, electrical continuity, and mechanical evaluations of prototype joints. Microstructural development along the solder and thick film interface, after isothermal solid state aging over a range of elevated temperatures and times, was quantified using microanalytical techniques. Flux residues on soldered samples were stressed (temperature-humidity aged) to identify potential corrosion problems. Mechanical tests also supported the development of a solder joint lifetime prediction model. Progress of this effort is summarized
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Compatibility of lead-free solders with lead containing surface finishes as a reliability issue in electronic assemblies
Enhanced performance goals and environmental restrictions have heightened the consideration for use of alternative solders as replacements for the traditional tin-lead (Sn-Pb) eutectic and near-eutectic alloys. However, the implementation of non-Pb bearing surface finishes may lag behind solder alloy development. A study was performed which examined the effect(s) of Pb contamination on the performance of Sn-Ag-Bi and Sn-Ag-Cu-Sb lead-free solders by the controlled addition of 63Sn-37Pb solder at levels of 0.5 {minus} 8.0 wt.%. Thermal analysis and ring-in-plug shear strength studies were conducted on bulk solder properties. Circuit board prototype studies centered on the performance of 20I/O SOIC gull wing joints. Both alloys exhibited declines in their melting temperatures with greater Sn-Pb additions. The ring-in-plug shear strength of the Sn-Ag-Cu-Sb solder increased slightly with Sn-Pb levels while the Sn-Ag-Bi alloy experienced a strength loss. The mechanical behavior of the SOIC (Small Outline Integrated Circuit) Sn-Ag-Bi solder joints reproduced the strength levels were insensitive to 10,106 thermal cycles. The Sn-Ag-Cu-Sb solder showed a slight decrease in the gull wing joint strengths that was sensitive to the Pb content of the surface finish
Coarsening of the Sn-Pb solder microstructure in constitutive model-based predictions of solder joint thermal mechanical fatigue
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Coarsening of the Sn-Pb Solder Microstructure in Constitutive Model-Based Predictions of Solder Joint Thermal Mechanical Fatigue
Thermal mechanical fatigue (TMF) is an important damage mechanism for solder joints exposed to cyclic temperature environments. Predicting the service reliability of solder joints exposed to such conditions requires two knowledge bases: first, the extent of fatigue damage incurred by the solder microstructure leading up to fatigue crack initiation, must be quantified in both time and space domains. Secondly, fatigue crack initiation and growth must be predicted since this metric determines, explicitly, the loss of solder joint functionality as it pertains to its mechanical fastening as well as electrical continuity roles. This paper will describe recent progress in a research effort to establish a microstructurally-based, constitutive model that predicts TMF deformation to 63Sn-37Pb solder in electronic solder joints up to the crack initiation step. The model is implemented using a finite element setting; therefore, the effects of both global and local thermal expansion mismatch conditions in the joint that would arise from temperature cycling
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