Integration of InP and InGaAs on 300 mm Si wafers using chemical mechanical planarization

Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In0.53Ga0.47As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300 mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In0.53Ga0.47As n-MOS channel layer on top of the planarized InP buffer

Deactivation of electrically supersaturated Te-doped InGaAs grown by MOCVD

Achieving and sustaining the highest doping level possible in InGaAs is critical for the reduction of contact resistance in future microelectronic applications. Tellurium (Te) is a very promising n-type dopant with high reported n-type doping densities. However, the stability of this dopant during post-growth thermal processing is unknown. Supersaturated Te-doped InGaAs layers were grown by MOCVD at 500 °C. The electrically active concentration of Te doping was 4.4 × 1019 cm−3 as grown. The thermal stability of the Te was investigated by studying the effect of post-growth annealing between 550 and 700 °C on the electrical activation. At all temperatures, the electrical activation decreased from its starting electron concentration of 4.4 × 1019 cm−3 down to 6–7 × 1018 cm−3. The rate of deactivation was measured at each temperature, and the activation energy for the deactivation process was determined to be 2.6 eV. The deactivation could be caused by either Te–Te clustering or a Te-point defect reaction. HAADF-STEM images showed no visible clustering or precipitation after deactivation. Based on previous ab initio calculations that suggest the VIII population increases as the Fermi level moves toward the conduction band, it is proposed that formation of isolated point defect complexes, possibly a Te–VIII complex, is associated with the deactivation process

GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, 8 108 cm 2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only on {111} Si planes, minimizing the interfacial energy and preventing the formation of antiphase boundaries

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

peer reviewedWe report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform

Heavily tellurium doped n-type InGaAs grown by MOCVD on 300 mm Si wafers

Tellurium has several remarkable properties that make it an attractive n-type dopant in III–V semiconductors, namely high incorporation and activation efficiency resulting in high achievable doping levels in combination with a low diffusion coefficient. However, it suffers from a strong memory effect related to its surfactant behavior that inhibits sharp junction interface formation. We report Te-doped In0.53Ga0.47As with an electron density of 8×1019 cm−3. The layers were grown by MOCVD on 300 mm Si wafers and were characterized by SIMS, XRD, Hall effect, and sheet resistivity mapping. The high active electron density and the excellent uniformity over the wafer surface make this process promising for selective regrowth of highly doped source and drain in VLSI

L g=80 -nm trigate quantum-well In0.53Ga0.47As metal–oxide–semiconductor field-effect transistors with Al2O3/HfO2 gate-stack

Abstract—We report on Lg = 80-nm trigate quantum- well InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs) with record combination of subthreshold swing, transconductance and ON-current performance. The device features a multilayer cap design, bilayer Al2O3/HfO2 (0.7/2 nm) gate-stack by atomic layer deposition and dry etched In0.53Ga0.47As fin. An Lg = 80-nm trigate MOSFET with fin-width (Wfin) = 30 nm and fin-height (Hfin) = 20 nm exhibits excellent performance, such as ON-resistance (RON) = 220 -μm, subthreshold swing (S) = 82 mV/dec, and drain-induced- barrier lowering = 10 mV/V at VDS = 0.5 V. Besides, the device exhibits record values of maximum transconductance (gm_max) = 1800 μS/μm and ION = 0.41 mA/μm at VDS = 0.5 V, and a record combination of gm_max and S in any III–V nonplanar MOSFET technology