Leakage current conduction in metal gate junctionless nanowire transistors

International audienceIn this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

International audienceIn this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators

Drain current local variability analysis in nanoscale junctionless FinFETs utilizing a compact model

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Threshold voltage of p-type triple-gate junctionless transistors

International audienceThe threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is studied experimentally using the transconductance derivative (dg$_m$ /dV$_g$) method, after correcting the drain current from the impact of series resistance. The effect of series resistance on the dg$_m$ /dV$_g$ behavior is highlighted. In the investigated devices, the high series resistance affects the dg$_m$ /dV$_g$ behavior more than the short-channel effects. The results show that, in addition to the flat-band voltage, for the first time two threshold voltages V$_{th1}$ and V$_{th2}$ are observed within the partial depletion region in devices with channel length varying from 95 to 25 nm. Numerical simulations of the holes density distribution reveal the absence of corner effects due to the unique bulk neutral conduction, whereas V$_{th1}$ and V$_{th2}$ correspond to the threshold voltages of the side gates and top gate, respectively. The correct extraction of the flat-band voltage has been confirmed with numerical simulations of the holes density distribution. Experimental measurements of p-type JLTs with variable being the fin width indicate that the threshold voltages V$_{th1}$ and V$_{th2}$ are due to the different interface states density at the side and top gates

Continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs

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