Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution

First wave of COVID-19 in Venezuela:Epidemiological, clinical, and paraclinical characteristics of first cases

The coronavirus disease 2019 (COVID-19) pandemic has particularly affected countries with weakened health services in Latin America, where proper patient management could be a critical step to address the epidemic. In this study, we aimed to characterize and identify which epidemiological, clinical, and paraclinical risk factors defined COVID-19 infection from the first confirmed cases through the first epidemic wave in Venezuela. A retrospective analysis of consecutive suspected cases of COVID-19 admitted to a sentinel hospital was carried out, including 576 patient cases subsequently confirmed for severe acute respiratory syndrome coronavirus 2 infection. Of these, 162 (28.1%) patients met the definition criteria for severe/critical disease, and 414 (71.2%) were classified as mild/moderate disease. The mean age was 47 (SD 16) years, the majority of which were men (59.5%), and the most frequent comorbidity was arterial hypertension (23.3%). The most common symptoms included fever (88.7%), headache (65.6%), and dry cough (63.9%). Severe/critical disease affected mostly older males with low schooling (p < 0.001). Similarly, higher levels of glycemia, urea, aminotransferases, total bilirubin, lactate dehydrogenase, and erythrocyte sedimentation rate were observed in severe/critical disease patients compared to those with mild/moderate disease. Overall mortality was 7.6% (44/576), with 41.7% (28/68) dying in hospital. We identified risk factors related to COVID-19 infection, which could help healthcare providers take appropriate measures and prevent severe clinical outcomes. Our results suggest that the mortality registered by this disease in Venezuela during the first epidemic wave was underestimated. An increase in fatalities is expected to occur in the coming months unless measures that are more effective are implemented to mitigate the epidemic while the vaccination process is ongoing

Salmonella enterica Serovar Typhimurium Lacking hfq Gene Confers Protective Immunity against Murine Typhoid

Salmonella enterica is an important enteric pathogen and its various serovars are involved in causing both systemic and intestinal diseases in humans and domestic animals. The emergence of multidrug-resistant strains of Salmonella leading to increased morbidity and mortality has further complicated its management. Live attenuated vaccines have been proven superior over killed or subunit vaccines due to their ability to induce protective immunity. Of the various strategies used for the generation of live attenuated vaccine strains, focus has gradually shifted towards manipulation of virulence regulator genes. Hfq is a RNA chaperon which mediates the binding of small RNAs to the mRNA and assists in post-transcriptional gene regulation in bacteria. In this study, we evaluated the efficacy of the Salmonella Typhimurium Δhfq strain as a candidate for live oral vaccine in murine model of typhoid fever. Salmonella hfq deletion mutant is highly attenuated in cell culture and animal model implying a significant role of Hfq in bacterial virulence. Oral immunization with the Salmonella hfq deletion mutant efficiently protects mice against subsequent oral challenge with virulent strain of Salmonella Typhimurium. Moreover, protection was induced upon both multiple as well as single dose of immunizations. The vaccine strain appears to be safe for use in pregnant mice and the protection is mediated by the increase in the number of CD4+ T lymphocytes upon vaccination. The levels of serum IgG and secretory-IgA in intestinal washes specific to lipopolysaccharide and outer membrane protein were significantly increased upon vaccination. Furthermore, hfq deletion mutant showed enhanced antigen presentation by dendritic cells compared to the wild type strain. Taken together, the studies in murine immunization model suggest that the Salmonella hfq deletion mutant can be a novel live oral vaccine candidate

Impact of aging phenomena on soft error susceptibility

In this paper we address the issue of analyzing the effects of negative bias temperature instability (NBTI) on ICs' soft error susceptibility. We show that NBTI reduces significantly the critical charge of nodes of both combinational and sequential circuits during their in-field operation. Furthermore, we prove that combinational circuits present a higher relative reduction of node critical charge than sequential ones. Therefore, as an IC ages, the soft-error susceptibility of its combinational parts will increase much more than that of its sequential parts. This poses new challenges to ICs' soft error susceptibility modeling, mandating a time dependent modeling (in contrast to the static modeling broadly considered till now), and a diverse time dependent modeling for their combinational and sequential parts. © 2011 IEEE

De l'effet destructeur d'un arrêt d'annulation sur des mesures non querellées, observations sous Conseil d'Etat, n° 19.250, 14 novembre 1978, Janssens et crts

SOMMAIRE : I. Les faits préalables à l'arrêt du 14 novembre 1978 / II. De l'effet de l'annulation d'une disposition réglementaire sur ses mesures d'application / III. Des recours querellant des mesures d'application d'une disposition réglementaire annulé

Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic

We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as Function-Inherent Codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches. © 2008 IEEE

On transistor level gate sizing for increased robustness to transient faults

In this paper we present a detailed analysis on how the critical charge (Q crit) of a circuit node, usually employed to evaluate the probability of transient fault (TF) occurrence as a consequence of a particle hit, depends on transistors' sizing. We derive an analytical model allowing us to calculate a node's Q crit given the size of the node's driving gate and fan-out gate(s), thus avoiding time costly electrical level simulations. We verified that such a model features an accuracy of the 97% with respect to electrical level simulations performed by HSPICE. Our proposed model shows that Q crit depends much more on the strength (conductance) of the gate driving the node, than on the node total capacitance. We also evaluated the impact of increasing the conductance of the driving gate on TFs' propagation, hence on Soft Error Susceptibility (SES). We found that such a conductance increase not only improves the TF robustness of the hardened node, but also that of the whole circuit. © 2005 IEEE

Accurate linear model for SET critical charge estimation

In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (Q-SET}). Our proposed model allows to calculate the Q-SET} of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that Q-SET} has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness. © 2006 IEEE

Low cost concurrent error detection strategy for the control logic of high performance microprocessors and its application to the instruction decoder

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs. © 2013 Springer Science+Business Media New York