Near-infrared study of new embedded clusters in the Carina complex

We analyse the nature of a sample of stellar overdensities that we found projected on the Carina complex. This study is based on 2MASS photometry and involves the photometry decontamination of field stars, elaboration of intrinsic colour-magnitude diagrams J$\times$(J-Ks), colour-colour diagrams (J-H)$\times$(H-Ks) and radial density profiles, in order to determine the structure and the main astrophysical parameters of the best candidates. The verification of an overdensity as an embedded cluster requires a CMD consistent with a PMS content and MS stars, if any. From these results, we are able to verify if they are, in fact, embedded clusters. The results were, in general, rewarding: in a sample of 101 overdensities, the analysis provided 15 candidates, of which three were previously catalogued as clusters (CCCP-Cl$\,$16, Treasure Chest and FSR$\,$1555), and the 12 remaining are discoveries that provided significant results, with ages not above 4.5$\,$Myr and distances compatible with the studied complex. The resulting values for the differential reddening of most candidates were relatively high, confirming that these clusters are still (partially or fully) embedded in the surrounding gas and dust, as a rule within a shell. Histograms with the distribution of the masses, ages and distances were also produced, to give an overview of the results. We conclude that all the 12 newly found embedded clusters are related to the Carina complex.Comment: 10 pages, 14 figures, accepted for publication in MNRA

A Flexible Implementation of a Matrix Laurent Series-Based 16-Point Fast Fourier and Hartley Transforms

This paper describes a flexible architecture for implementing a new fast computation of the discrete Fourier and Hartley transforms, which is based on a matrix Laurent series. The device calculates the transforms based on a single bit selection operator. The hardware structure and synthesis are presented, which handled a 16-point fast transform in 65 nsec, with a Xilinx SPARTAN 3E device.Comment: 4 pages, 4 figures. IEEE VI Southern Programmable Logic Conference 201