93 research outputs found

    THEORY AND DESIGN OF T-ERROR CORRECTING D-ERROR DETECTING (D GREATER-THAN T) AND ALL UNIDIRECTIONAL ERROR DETECTING CODES

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    In this paper, the fundamental theory of t-error correcting/d-error detecting (d > t) and all unidirectional error detecting (t-EC/d-ED/AUED) codes is given. A method for construction of systematic t-EC/d-ED/AUED codes is presented. The encoding/decoding algorithms for these codes and their implementation are also described

    High-speed parallel-prefix VLSI Ling adders

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    Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance

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    Novel single and double output TSC CMOS checkers for m-out-of-n codes

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    This paper presents a novel method for designing Totally Self-Checking (TSC) m-out-of-n code checkers taking into account a realistic fault model including stuck-at, transistor stuck-on, transistor stuck-open, resistive bridging faults and breaks. The proposed design method is the first method in the open literature that takes into account a realistic fault model and can be applied for most practical values of m and n. Apart from the above the proposed checkers are very compact and very fast. The single output checkers are near optimal with respect to the number of transistors required for their implementation. Another benefit of the proposed TSC checkers is that all faults are tested by a very small set of single pattern tests, thus the probability of achieving the TSC goal is greater than in checkers requiring two-pattern tests. The single output TSC checkers proposed in this paper are the first known single output TSC checkers for m-out-of-n codes
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