Self-aligned contacts for 10nm FDSOI node : from device to circuit evaluation

We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optmimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications

MOS technology for quantum computing: recent progress and perspectives for scaling up

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Wafer-level characterization of industrial grade Si-based qubit devices.

International audienceEfforts in improving the quality and number of solid-state spin qubits within a single device are currently hindered by the lack of large-scale characterization tools. Here, we present a characterization methodology for bi-linear quantum-dot array structures using transistor-like metrics measured at both 300K and 1K, at the wafer-level. The quantum-dot measurements at 1K are crucial to obtain specific information about the spin-qubit confinement and provide meaningful feedbacks to the process integration. With this large-scale characterization, we study the correlations between (i) 300K and 1K transistor-like metrics, and (ii) 1K transistor-like and quantum-dot properties. We discuss the correlations and how they can speed up the characterization at the wafer scale

A single hole spin with enhanced coherence in natural silicon

International audienceAbstract Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however, renders these qubits generally vulnerable to electrical noise, which limits their coherence time. Here we report on a spin–orbit qubit consisting of a single hole electrostatically confined in a natural silicon metal-oxide-semiconductor device. By varying the magnetic field orientation, we reveal the existence of operation sweet spots where the impact of charge noise is minimized while preserving an efficient electric-dipole spin control. We correspondingly observe an extension of the Hahn-echo coherence time up to 88 μs, exceeding by an order of magnitude existing values reported for hole spin qubits, and approaching the state-of-the-art for electron spin qubits with synthetic spin–orbit coupling in isotopically purified silicon. Our finding enhances the prospects of silicon-based hole spin qubits for scalable quantum information processing

Gate-based high fidelity spin readout in a CMOS device

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Material and integration challenges for large scale Si quantum computing

International audienceSi spin qubits are very promising to enable large scale quantum computing as they are fast, of high quality and small. However, they are still lagging behind in terms of number of qubits. Indeed there are material and integration challenges to be tackled before fully expressing their potential

Challenges and perspectives in the modeling of spin qubits

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