On the Continuous-Time Model for Nonlinear- Memory Modeling of RF Power Amplifiers

International audienceThe RF front-end in modern communication systems is faced with variable envelope and large bandwidth signals (including desired signals and large interferers), which require the behavioral model of the amplifying unit (either in Tx or Rx) to accurately account for nonlinear memory effects. Important advancements have been made on the subject; however it is still challenging to derive a model that performs equally well with all possible input stimuli. This paper gives a concise overview of the recent developments that have been made on the continuous-time modeling approach for the behavioral modeling of nonlinear memory in power amplifiers, as opposed to the explicit discrete-time modeling approach

Contribution a la creation d'outils de CAO des circuits non-lineaires microondes

SIGLECNRS T Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Accurate and Fast Simulation of Noise in RF Transceivers

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On the Cyclostationary Noise Analysis in Large RF Integrated Circuits

International audienceThis paper examines the issue of noise analysis in RF integrated circuits (RFICs). The complexity of the RFIC grows constantly, with transistor counts now into the thousands or tens of thousands. Since RFICs are driven by large-signal multitone excitations, the stochastic noise process in these circuits is cyclostationary. This combination of large device count and noise cyclostationarity makes noise analysis in RFICs a time-consuming task. Simulation algorithms that minimize computer memory consumption and computation cost are thus necessary. There is a consensus now that harmonic balance is the most appropriate circuit equation solution method for multitone analysis of RF circuits. The paper thus gives a comprehensive description of a harmonic balance-based algorithm for computing the circuit noise response, showing how it effectively accounts for all types of cyclostationary noise sources supported by modern compact device models. The algorithm has been implemented in a commercial simulator and shows good capabilities for the analysis of full transceiver circuits within reasonable computer memory occupancy and simulation times

Modeling long term memory effects in microwave power amplifiers for system level simulations

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Compressed Transient analysis speeds up the periodic steady state of nonlinear microwave circuits

International audienceHarmonic Balance is nowadays the most efficient method for the periodic steady state analysis of microwave circuits. Unfortunately this method cannot conveniently handle realistic wide band input signals, because its computation time grows rapidly with the number of harmonics. A new method is proposed which resolves the above mentioned limitation of the Harmonic Balance. A substantial computation time saving is obtained with respect to the Harmonic Balance

A Two-Kernel Nonlinear Impulse Response Model for Handling Long Term Memory Effects in RF and Microwave Solid State Circuits

International audienceAccurate modeling of the memory effects in nonlinear RF and microwave devices is of prime importance in the design process for the new generations of communications systems. This is particularly important for the design of power amplifier, predistorter and linearizer, and the prediction of system intermodulation distortion as well as power budget. This paper extends previous works and provides a comprehensive mathematical foundation for envelope-domain and band-pass nonlinear impulse response of RF and microwave blocs. The new model shows significant accuracy improvements in modeling long-term memory effects, especially self-heating. Besides the paper presents a new kernel identification technique that is faster and more accurate as it requires only frequency-domain measurements or harmonic-balance simulatio

A piecewise Transistor-Level Simulation Technique for the Steady State and Phase Noise Analysis of Integer N PLLs

International audiencePrint Request Permissions Save to Project Brute force transistor-level simulation of PLL is precise but suffers long simulation time and convergence problems, both with time domain and harmonic-balance techniques. On the other hand common behavioral phase domain simulation is rapid but does not consider the non-idealities at transistor-level. In this paper we propose a piecewise transistor-level simulation method, which stands between the two above approaches, and combines the advantages of both. In the proposed method, a hierarchical simulation process is applied to compute an accurate steady state, and a small-signal model is created for phase noise calculation. The phase noise is obtained rapidly and accurately