A piecewise Transistor-Level Simulation Technique for the Steady State and Phase Noise Analysis of Integer N PLLs

Abstract

International audiencePrint Request Permissions Save to Project Brute force transistor-level simulation of PLL is precise but suffers long simulation time and convergence problems, both with time domain and harmonic-balance techniques. On the other hand common behavioral phase domain simulation is rapid but does not consider the non-idealities at transistor-level. In this paper we propose a piecewise transistor-level simulation method, which stands between the two above approaches, and combines the advantages of both. In the proposed method, a hierarchical simulation process is applied to compute an accurate steady state, and a small-signal model is created for phase noise calculation. The phase noise is obtained rapidly and accurately