A generic review of the Acanthaclisine antlions based on larvae (Neuroptera: Myrmeleontidae)

The tribe Acanthaclisini Navas contains 14 described genera which we recognize as valid. We have reared larvae of 8 of these (Acanthaclisis Rambur, Centroclisis Navas, Fadrina Navas, Paranthaclisis Banks, Phanoclisis Banks, Synclisis Navas, Syngenes Kolbe, and Vella Navas). In addition, we have studied preserved larvae from Australia which probably represent the genus Heoclisis Navas. This represents the majority of the taxa, lacking only the small genera Avia Navas, Cosina Navas, Madrasta Navas, Mestressa Navas, and Stiphroneuria Gerstaecker. Studies of these larvae have revealed structural differences, especially of the mandible, which we have employed to provide identification of these genera by means of descriptions, keys, and illustrations. Also, since no modern key exists, we are providing a key to the genera based on adults which will provide some further insight on the generic relationships. Observations on the tribal differences of Myrmeleontidae based on larvae are made with a preliminary key to the known tribes

Multiplexing architecture for mixed-signal CMOS fuzzy controllers

Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the advantages of an analogue implementation, while allowing a marked increment in system complexity, is presented.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

A mixed-signal fuzzy controller and its application to soft start of DC motors

Presents a mixed-signal fuzzy controller chip and its application to control of DC motors. The controller is based on a multiplexed architecture presented by the authors (1998), where building blocks are also described. We focus here on showing experimental results from an example implementation of this architecture as well as on illustrating its performance in an application that has been proposed and developed. The presented chip implements 64 rules, much more than the reported pure analog monolithic fuzzy controllers, while preserving most of their advantages. Specifically, the measured input-output delay is around 500 ns for a power consumption of 16 mW and the chip area (without pads) is 2.65 mm/sup 2/. In the presented application, sensed motor speed and current are the controller input, while it determines the proper duty cycle to a PWM control circuit for the DC-DC converter that powers the motor drive. Experimental results of this application are also presented.Comisión Interministerial de Ciencia y Tecnología TIC99-082

A multiplexed mixed-signal fuzzy architecture

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal

A finitely generated, locally indicable group with no faithful action by C^1 diffeomorphisms of the interval

According to Thurston's stability theorem, every group of C^1 diffeomorphisms of the closed interval is locally indicable (.e., every finitely generated subgroup factors through Z). We show that, even for finitely generated groups, the converse of this statement is not true. More precisely, we show that the semi-direct product between F_2 an Z^2, although locally indicable, does not embed into Diff_+^1 (]0,1[). (Here F_2 is any free subgroup of SL(2,Z), and its action on Z^2 is the projective one.) Moreover, we show that for every non-solvable subgroup G of SL(2,Z), the semi-direct product between G and Z^2 does not embed into Diff^1_+(S^1).Comment: 8 pages, no figur

A modular CMOS analog fuzzy controller

The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy chips with optimum speed/power figures. This paper presents a sixteen rules-two inputs analog fuzzy controller in a CMOS 1 /spl mu/m single-poly technology based on building blocks implementations previously proposed by the authors (1995). However, such building blocks are rearranged here to get a highly modular architecture organized from two high level blocks: the label block and the rule block. In addition, sharing of membership function circuits allows a compact design with low area and power consumption and its highly modular architecture will permit to increase the number of inputs and rules in future chips with hardly design effort. The paper includes measurements from a silicon prototype of the controller

A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8