A CMOS self-triggered gated integrator circuit for SiPM readout in SPECT applications

Energy resolution plays a major role in multitracer SPECT detectors, as spectral lines emitted by different radionuclides have to be distinguished. In the electronic circuit for the readout of SiPMs used in a SPECT system, the processing filter choice is therefore essential to provide the best achievable energy resolution. Gated integrator filter was identified as an excellent candidate for this kind of application, mainly thanks to its capability to reduce ballistic deficit in the signal processing, allowing for a quasi-complete light collection with a filtering time considerably shorter with respect to the ones needed by time-invariant circuits. A single-channel prototype circuit in CMOS 0.35 μm technology was developed to validate preliminary studies. The circuit features a current buffer input stage with the possibility to tune the input voltage in a 1 V range with 6 bit resolution and a filtering section to integrate the signal rejecting the baseline component originated by the dark count current of the SiPM. A discriminator block recognises the arrival of the signal and initiates the integration phase; a control section generates the gating interval, selectable in a range between 80 ns and 15 μs to cope with various scintillator types, and manages the different timing phases of the circuit. A comparison between the energy resolution achievable using both a time invariant RC filter and a gated integrator one is done, showing, for the latter, a better expected energy resolution performance at the 140 keV 99mTc peak. Preliminary experimental results of the prototype when coupled to a SiPM are reported

A front-end stage with signal compression capability for XFEL detectors

In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range

Technical design of a new bone conduction implant (BCI) system

Objective: The objective of this study is to describe the technical design and verify the technical performance of a new bone conduction implant (BCI) system. Design: The BCI consists of an external audio processor and an implanted unit called the bridging bone conductor. These two units use an inductive link to communicate with each other through the intact skin in order to drive an implanted transducer. Study sample: In this study, the design of the full BCI system has been described and verified on a skull simulator and on real patients. Results: It was found that the maximum output force (peak 107 dB re 1 N) of the BCI is robust for skin thickness range of 2-8 mm and that the total harmonic distortion is below 8% in the speech frequency range for 70 dB input sound pressure level. The current consumption is 7.5 mA, which corresponds to 5-7 days use with a single battery. Conclusions: This study shows that the BCI is a robust design that gives a sufficiently high output and an excellent sound quality for the hearing rehabilitation of indicated patients

First operation of a DSSC hybrid 2D Soft X-ray imager with 4.5 MHz frame rate

The DSSC (DEPFET Sensor with Signal Compression) collaboration develops a hybrid pixelated X-Ray photon detector with 4.5 MHz frame rate and immediate amplitude digitization for experiments at the European XFEL. We present the first full format 14.9Ã\u9714 mm2F1 pixel readout ASIC for the DSSC detector. The readout architecture is specially adapted to the burst structure of the XFEL (bursts of 2880 pulses spaced by down to 220 ns at a rate of 10 Hz) by in-pixel digitization and digital hit data storage and data transfer during the burst gaps. The readout ASIC contains 64Ã\u9764 pixels of 229Ã\u97204 μm2size and includes per pixel two low noise front-end versions for DEPFET and silicon drift detectors (SDD), a single-slope 8-bit ADC and local memory. Measurements using the F1 ASIC and a matching mini-SDD sensor matrix are shown

The front-end chip of the SuperB SVT detector

The asymmetric e(+) e(-) collider SuperB is designed to deliver a high luminosity, greater than 10(36) cm(-2) S-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

The latest advances in the design and characterization of several pixel sensors developed to satisfy the very demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker will be presented in this paper. The SuperB machine is an electron positron collider operating at the ϒ(4S)ϒ(4S) peak to be built in the very near future by the Cabibbo Lab consortium. A pixel detector based on extremely thin, radiation hard devices able to cope with rate in the tens of MHz/cm^2 range will be the optimal solution for the upgrade of the inner layer of the SuperB tracking system. At present several options with different levels of maturity are being investigated to understand advantages and potential issues of the different technologies: thin hybrid pixels, Deep N-Well CMOS MAPS, INMAPS CMOS MAPS featuring a quadruple well and high resistivity substrates and CMOS MAPS realized with Vertical Integration technology. The newest results from beam test, the outcomes of the radiation damage studies and the laboratory characterization of the latest prototypes will be reported

Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10–15um in both coordinates, low material budget <1%X0, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper