Fast and Accurate Power Estimation of FPGA DSP Components Based on High-level Switching Activity Models

When designing DSP circuits, it is important to predict their power consumption early in the design flow in order to reduce the repetition of time consuming design phases. High-level modelling is required for fast power estimation when a design is modified at the algorithm level. This paper presents a novel high-level analytical approach to estimate logic power consumption of arithmetic components implemented in FPGAs. In particular, models of adders and multipliers are presented in detail. The proposed methodology considers input signal correlation and glitching produced inside the component. It is based on an analytical computation of the switching activity in the component which takes into account the component architecture. The complete model can estimate the power consumption for any given clock frequency, signal statistics and operands’ word-lengths. Compared to other proposed power estimation methods, the number of circuit simulations needed for characterizing the power model of the component is highly reduced. The accuracy of the model is within 10% of low-level power estimates given by the tool XPower, and it achieves better overall performance

Advanced Power Estimation Techniques

This chapter describes a methodology and techniques for power estimation and analysis at behavioral, register-transfer and gate levels of design abstraction. The major components of the proposed methodology are survey sampling techniques, probabilistic compaction techniques, RTL co-simulation engine, power macro-modeling, and high-level power estimation. 1 Statistical Sampling Existing power estimation techniques at the gate level and the circuit level can be classi ed into two classes: static and dynamic. Static techniques [21, 5,15,13] rely on statistical information (such as the mean activity of the input signals and their correlations) about the input stream to estimate the internal switching activity of the circuit. While these are very e cient, their main limitation is that they cannot accurately capture factors such as slew rates, glitch generation and propagation, DC ghting, etc. Dynamic techniques [7, 3] explicitly simulate the circuit under a \typical " input vector stream. They can be applied at both the circuit and gate levels. Their mai

Smart Videocapsule for Early Diagnosis of Colorectal Cancer: Toward Embedded Image Analysis

International audienceFor the last 20 years, wireless videocapsule technology has triggered alot of interest in the gastroenterologist community for the non-invasive early detectionof various gastrointestinal pathologies (ulcers, Chrones disease, polyp detection,etc.). Nevertheless, in most of the European countries videocapsules are notyet considered as a systematic valid alternative to classic endoscopies and colonoscopies.Main reasons are in the existing technological limitations of videocapsulesthat are of two kinds: (i) A limited battery life-time (8 hours usually ensured bythe manufacturer) that does not allow a complete imaging of the gastro intestinaltract, and (ii) the limited performance of the device in terms of detection rate of particularstructures like polyps for instance which degenerations are at the origin ofcolorectal cancer. To overpass these limitations, main idea of our work is to developa generation of smart videocapsules that takes advantage of the constant progress inelectronics and most precisely in embedded signal processing tasks. In this Chapter,we give first a detailed overview of the most recent state-of-the-art related tovideocapsules from the technological perspective in order to clearly positioned ourwork among the existing products and on going projects. In a second time, we proposea synthetic recall of the Cyclope project in the framework of which we arestudying different strategies to improve the performance of current videocapsules inthe particular context of the early diagnosis of colorectal cancer (polyp detection).We then propose a particular focus on the design optimization of the proposed algorithms from an electronic perspective. Most precisely, we give concrete elementsand quantitative estimation (time processing, embedding performance, etc.) to showthat embedding of the signal processing IP inside the videocapsule is feasible consideringthe most recent FPGA-platform performance, and that such an integrationcan bring a positive balance in terms of energy consumption by drastically reducingthe amount of transmitted data