Mu2e Run I Sensitivity Projections for the Neutrinoless μ− → e− Conversion Search in Aluminum

The Mu2e experiment at Fermilab will search for the neutrinoless μ−→e− conversion in the field of an aluminum nucleus. The Mu2e data-taking plan assumes two running periods, Run I and Run II, separated by an approximately two-year-long shutdown. This paper presents an estimate of the expected Mu2e Run I search sensitivity and includes a detailed discussion of the background sources, uncertainties of their prediction, analysis procedures, and the optimization of the experimental sensitivity. The expected Run I 5σ discovery sensitivity is Rμe=1.2×10−15, with a total expected background of 0.11±0.03 events. In the absence of a signal, the expected upper limit is Rμe<6.2×10−16 at 90% CL. This represents a three order of magnitude improvement over the current experimental limit of Rμe<7×10−13 at 90% CL set by the SINDRUM II experiment

Mu2e Run I Sensitivity Projections for the Neutrinoless Conversion Search in Aluminum

The Mu2e experiment at Fermilab will search for the neutrinoless μ−→e− conversion in the field of an aluminum nucleus. The Mu2e data-taking plan assumes two running periods, Run I and Run II, separated by an approximately two-year-long shutdown. This paper presents an estimate of the expected Mu2e Run I search sensitivity and includes a detailed discussion of the background sources, uncertainties of their prediction, analysis procedures, and the optimization of the experimental sensitivity. The expected Run I 5σ discovery sensitivity is Rμe=1.2×10−15, with a total expected background of 0.11±0.03 events. In the absence of a signal, the expected upper limit is Rμe6.2×10−16 at 90% CL. This represents a three order of magnitude improvement over the current experimental limit of Rμe7×10−13 at 90% CL set by the SINDRUM II experiment

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed