Food environments and obesity: a geospatial analysis of the South Asia Biobank, income and sex inequalities.

Introduction: In low-middle income countries (LMICs) the role of food environments on obesity has been understudied. We address this gap by 1) examining the effect of food environments on adults' body size (BMI, waist circumference) and obesity; 2) measuring the heterogeneity of such effects by income and sex. Methods: This cross-sectional study analysed South Asia Biobank surveillance and environment mapping data for 12,167 adults collected between 2018 and 2020 from 33 surveillance sites in Bangladesh and Sri Lanka. Individual-level data (demographic, socio-economic, and health characteristics) were combined with exposure to healthy and unhealthy food environments measured with geolocations of food outlets (obtained through ground-truth surveys) within 300 m buffer zones around participants' homes. Multivariate regression models were used to assess association of exposure to healthy and unhealthy food environments on waist circumference, BMI, and probability of obesity for the total sample and stratified by sex and income. Findings: The presence of a higher share of supermarkets in the neighbourhood was associated with a reduction in body size (BMI, β = - 3∙23; p < 0∙0001, and waist circumference, β = -5∙99; p = 0∙0212) and obesity (Average Marginal Effect (AME): -0∙18; p = 0∙0009). High share of fast-food restaurants in the neighbourhood was not significantly associated with body size, but it significantly increased the probability of obesity measured by BMI (AME: 0∙09; p = 0∙0234) and waist circumference (AME: 0∙21; p = 0∙0021). These effects were stronger among females and low-income individuals. Interpretation: The results suggest the availability of fast-food outlets influences obesity, especially among female and lower-income groups. The availability of supermarkets is associated with reduced body size and obesity, but their effects do not outweigh the role of fast-food outlets. Policies should target food environments to promote better diets and reduce obesity

Schemes for avoiding starvation in transactional memory systems

Transactional memory systems trade ease of programming with run-time performance losses in handling transactions. This paper focuses on starvation effects that show up in systems where unordered transactions are committed on a demand-driven basis. Such simple commit arbitration policies are prone to starvation. The design issues for commit arbitration policies are analyzed and novel policies that reduce the amount of wasted computation due to roll-back and, most important, that avoid starvation are proposed. We analyze in detail how to incorporate them in the transactional coherence and consistency protocol as well as a scalable version of it. The proposed schemes are shown to have no impact on the common-case performance and add quite modest complexity to the baseline protocol. Copyright (C) 2008 John Wiley & Sons, Ltd

Evaluation of patient’s satisfaction in the surgical units in a tertiary care public hospital

Introduction: In the modern era, it is not only the right of every patient to demand best possible medical care in Government runs Hospitals, but it is the moral and legal obligation of every health care provider as well, to deliver his optimum efforts to the entire satisfaction of the patient. Methods: A pre formed questionnaire and personal interview of 350 patients was carried out to determine the level of satisfaction among patients. Results: Most of the patients were found to be more than satisfied in most of the categories of questions asked. Conclusion: Overall assessment of the whole process through this study gave us an opportunity to find loopholes and deficiencies in our services for any future remedial action. The response given by the patients at the end of the data collected enabled us to make any suggestions so as to improve the quality of the services rendered at the hospital

Efficient Management of Speculative Data in Hardware Transactional Memory Systems

Transactional memory systems promise to simplify parallel programming by avoiding deadlock, livelock, and serialization problems through optimistic, concurrent execution of code segments that potentially can have data conflicts with each other. Data conflict detection in proposed hardware transactional memory systems is done by associating a read bit with each cache block that is set when a block is speculatively read. However, since the set of blocks that have been speculatively read - the read set - has to be maintained until the transaction commits, one can often not replace a block that has been speculatively read. This leads to poor utilization of the private caches in a multi-core system. We propose a new scheme for managing the read set in hardware transactional memory systems. The novel insight is that only the addresses of the speculatively read blocks are needed for conflict detection but not the data. As a result, there is an opportunity to reduce the space needed to keep track of speculatively read blocks by B/A, where B is the block size and A is the block address. Assuming that B is 32 bytes and A is 32 bits, there is an eightfold space saving due to this. This paper presents a novel design for leveraging this opportunity and evaluates a concept that uses a Bloom filter to hash the addresses of the read set into a structure. We find that the proposed scheme utilizes the private cache more efficiently in a typical system configuration

Efficient Management of Speculative Data in Hardware Transactional Memory Systems

Transactional memory systems promise to simplify parallel programming by avoiding deadlock, livelock, and serialization problems through optimistic, concurrent execution of code segments that potentially can have data conflicts with each other. Data conflict detection in proposed hardware transactional memory systems is done by associating a read bit with each cache block that is set when a block is speculatively read. However, since the set of blocks that have been speculatively read – the read set – has to be maintained until the transaction commits, one can often not replace a block that has been speculatively read. This leads to poor utilization of the private caches in a multi-core system. We propose a new scheme for managing the read set in hardware transactional memory systems. The novel insight is that unlike in proposed systems, where data in a block that is speculatively read is kept in cache, we note that only the address of that block is needed. As a result, there is an opportunity to reduce the space needed to keep track of speculatively read blocks by B/A, where B is the block size and A is the block address. Assuming that B is 32 bytes and A is 32 bits, there is an eightfold space saving due to this. This paper presents a novel design for leveraging this opportunity and evaluates a concept that uses a Bloom filter to hash the addresses of the read set into a structure. We find that the proposed scheme utilizes the private cache more efficiently and removes around 90% of the private cache overflows

LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems

Chalmers Library Link Resolver(opens in a new window)|View at Publisher| Export | Download | Add to List | More... ACM International Conference Proceeding Series 2010, Article number 1882460 2nd International Forum on Next Generation Multicore/Manycore Technologies, IFMT'2010, Co-located with the 37th International Symposium on Computer Architecture, ISCA 2010; Saint-Malo; France; 19 June 2010 through 19 June 2010; Code 83375 LV*: A class of lazy versioning HTMs for low-cost integration of transactional memory systems (Conference Paper) Negi, A. , Waliullah, M.M. , Stenstrom, P. Chalmers University of Technology, Gothenburg, Sweden View references (29) Abstract Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been deployed in any machine yet, experience of using it is limited. While software transactional memory implementations exist, they are too slow to provide useful experience. Existing hardware transactional memory implementations, on the other hand, can provide the efficiency required but they require a significant effort to integrate in cache coherence infrastructures or freeze critical policy parameters. This paper proposes the LV* (lazy versioning and eager/lazy conflict resolution) class of hardware transactional memory protocols. This class of protocols has been implemented with ease of deployment in mind. LV* can be integrated with low additional complexity in standard snoopy-cache MESI-protocols and can be accommodated in a directory-based cache coherence infrastructure. Since the optimal conflict resolution policy (lazy or eager) depends on transactional characteristics of workloads, LV* supports a set of conflict resolution policies that range from LazEr - a family of Lazy versioning Eager conflict resolution protocols - to LL-MESI which provides lazy resolution. We show that LV* can be hosted in a MESI protocol through straightforward extensions and that the flexibility in the choice of conflict resolution strategy has a significant impact on performance