Conception et optimisation d’architectures reconfigurables de type FPGA

In the early stages of system design, system architects often choose between FPGAs and ASICs implementations. Such decisions are based on the differences between these implementations in terms of performance, power consumptions and cost, which is related to the silicon area and the target production volume. For circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGA (LUT-based) and ASICs (via standard cells) is on average 40. The ratio of critical path delay is roughly 3 to 4, and approximately 12 times for the dynamic power consumption. This gap is due to the FPGA interconnect network which is the dominantfactor in terms of FPGA area (90%) and power dissipation (65%). In order to remain attractive, FPGA fabric must offer a good tradeoff between flexibility, performances and cost. These factors are linked to quality of the architecture, quality of the CAD tools and quality of the physical design. The subject of this dissertation is the exploration of methods and techniques to find the best tradeoff.The first part deals with the automatic design of domain-specific reconfigurable fabrics with Mesh topology. Developing a domain-specific reconfigurable fabric has taken traditionally too much time and effort to be worthwhile. We are alleviating these design costs by automating the process of creating domain specific reconfigurable fabrics.We develop a technology-independent layout generator which is easily adapted to any standard cell library geometry and to any process rules. We have generated an SRAM Mesh-based Redundant FPGA Core with fine granularity that integrates an error-detector system for SEU mitigation. The design was successfully migrated and taped out in 0.12 um 6-metal layer CMOS process from ST.The second part focuses on the development and the design of new Multilevel Hierarchical FPGA (MFPGA) architecture based on the Butterfly Fat Tree topology . Since the interconnect is the dominant resource in FPGA, we believe that it is the key to reduce FPGA area, hence to increase performances and decrease power consumption. Weexplore the effect of different architecture parameters (Rent’s parameter, cluster sizes) to satisfy specific applicative constraints of logic density. Thanks to the good balancing between logic and interconnect resources, MFPGA achieves a gain of 54% in term of area compared to the common Clustered Mesh-based FPGA architecture. Finally, we propose a physical floorplanning technique for MFPGA to illustrate layout feasibility, scalability and density.La question du choix d’implémentations FPGA ou ASIC se pose dès les premiers stades de conception des circuits intégrés. De telles décisions sont basées sur les différences en termes de performances, consommation électrique et du coût lié à la surface de silicium et au volume de production.Un FPGA est 3 à 4 fois plus lent et consomme environ 12 fois plus qu’un ASIC. Cet écart est dû au réseau d’interconnexion programmable qui représente le facteur dominant du FPGA en terme de surface (90%) et en terme de consommation électrique (65%). Les circuits FPGAs doivent fournir un bon compromis entre flexibilité, performances et coût pour rester dans la course du marché des semi-conducteurs. Ces facteurs sont fortement liées à la qualité de l’architecture du FPGA, la qualité des outils de CAO et la qualité de la conception physique. L’objet de cette thèse est d’explorer les méthodes et les techniques pour trouver le meilleur compromis.La première partie traite la conception automatisée de cicuits reconfigurables spécifiques à un domaine d’application. Nous essayons de baisser les coûts de conception en automatisant le processus de développement des dessins des masques. Le générateur développé est indépendant de la technologie cible et peut être adaptés à n’importe quelle bibliothèque de cellules précaractérisées.Ce générateur a permis la création d’une matrice FPGA à base de cellules SRAMs. Cette matrice est équipée d’un système de détection d’erreur pour l’atténuation des effets SEU et offre un accès aléatoire à la mémoire de configuration. Un prototype a été fabriqué avec succès en technologie CMOS 0.12μde STmicroelectronics.La deuxième partie décrit le développement d’un FPGA avec une architecture arborescente nommée MFPGA. Nous avons exploré l’effet des différents paramètres de cette architecture (capacité des clusters, paramètre de Rent etc.) sur la densité logique du FPGA. Grâce à un bon équilibrage entre les ressources logiques et les ressources d’interconnexion, MFPGA réalise un gain de 54% en terme de surface par rapport à une architecture matricielle de référence. Finalement, vu la complexité de conception physique des structures arborescentes, nous avons proposé une technique de mise à plat et de construction physique pour MFPGA pour illustrer la faisabilité, la généricité et la densité de cette architecture

Design and optimization of reconfigurable architectures (the FPGA family)

La question du choix d implémentations FPGA ou ASIC se pose dès les premiers stades de conception des circuits intégrés. De telles décisions sont basées sur les différences en termes de performances, consommation électrique et du coût lié à la surface de silicium et au volume de production.Un FPGA est 3 à 4 fois plus lent et consomme environ 12 fois plus qu un ASIC. Cet écart est dû au réseau d interconnexion programmable qui représente le facteur dominant du FPGA en terme de surface (90%) et en terme de consommation électrique (65%). Les circuits FPGAs doivent fournir un bon compromis entre flexibilité, performances et coût pour rester dans la course du marché des semi-conducteurs. Ces facteurs sont fortement liées à la qualité de l architecture du FPGA, la qualité des outils de CAO et la qualité de la conception physique. L objet de cette thèse est d explorer les méthodes et les techniques pour trouver le meilleur compromis. La première partie traite la conception automatisée de cicuits reconfigurables spécifiques à un domaine d application. Nous essayons de baisser les coûts de conception en automatisant le processus de développement des dessins des masques. Le générateur développé est indépendant de la technologie cible et peut être adaptés à n importe quelle bibliothèque de cellules précaractérisées. Ce générateur a permis la création d une matrice FPGA à base de cellules SRAMs. Cette matrice est équipée d un système de détection d erreur pour l atténuation des effets SEU et offre un accès aléatoire à la mémoire de configuration. Un prototype a été fabriqué avec succès en technologie CMOS 0.12 de STmicroelectronics. La deuxième partie décrit le développement d un FPGA avec une architecture arborescente nommée MFPGA. Nous avons exploré l effet des différents paramètres de cette architecture (capacité des clusters, paramètre de Rent etc.) sur la densité logique du FPGA. Grâce à un bon équilibrage entre les ressources logiques et les ressources d interconnexion, MFPGA réalise un gain de 54% en terme de surface par rapport à une architecture matricielle de référence. Finalement, vu la complexité de conception physique des structures arborescentes, nous avons proposé une technique de mise à plat et de construction physique pour MFPGA pour illustrer la faisabilité, la généricité et la densité de cette architecture.In the early stages of system design, system architects often choose between FPGAs and ASICs implementations. Such decisions are based on the differences between these implementations in terms of performance, power consumptions and cost, which is related to the silicon area and the target production volume. For circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGA (LUT-based) and ASICs (via standard cells) is on average 40. The ratio of critical path delay is roughly 3 to 4, and approximately 12 times for the dynamic power consumption. This gap is due to the FPGA interconnect network which is the dominant factor in terms of FPGA area (90%) and power dissipation (65%). In order to remain attractive, FPGA fabric must offer a good tradeoff between flexibility, performances and cost. These factors are linked to quality of the architecture, quality of the CAD tools and quality of the physical design. The subject of this dissertation is the exploration ofmethods and techniques to find the best tradeoff. The first part deals with the automatic design of domain-specific reconfigurable fabrics with Mesh topology. Developing a domain-specific reconfigurable fabric has taken traditionally too much time and effort to be worthwhile. We are alleviating these design costs by automating the process of creating domain specific reconfigurable fabrics. We develop a technology-independent layout generator which is easily adapted to any standard cell library geometry and to any process rules. We have generated an SRAM Mesh-based Redundant FPGA Core with fine granularity that integrates an error-detector system for SEU mitigation. The design was successfully migrated and taped out in 0.12 um 6-metal layer CMOS process from ST. The second part focuses on the development and the design of new Multilevel Hierarchical FPGA (MFPGA) architecture based on the Butterfly Fat Tree topology . Since the interconnect is the dominant resource in FPGA, we believe that it is the key to reduce FPGA area, hence to increase performances and decrease power consumption. We explore the effect of different architecture parameters (Rent s parameter, cluster sizes) to satisfy specific applicative constraints of logic density. Thanks to the good balancing between logic and interconnect resources, MFPGA achieves a gain of 54% in term of area compared to the common Clustered Mesh-based FPGA architecture. Finally, we propose a physical floorplanning technique for MFPGA to illustrate layout feasibility, scalability and density.PARIS-BIUSJ-Mathématiques rech (751052111) / SudocSudocFranceF

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

International audienceWe present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%

A new Multilevel Hierarchical MFPGA and its suitable configuration tools

In this paper we evaluate a new multilevel hierarchical MF-PGA. The specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller area

Generic Techniques and CAD tools for automated generation of FPGA Layout

International audienceThis paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130 nm technology

Hierarchical FPGA clustering to improve routability

International audienceIn this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing tools

Performances comparison between multilevel hierarchical and mesh FPGA interconnects

International audienceIn this paper we evaluate a new multilevel hierarchical FPGA (MFPGA). The specific architecture includes two unidirectional programmable networks: A downward network based on the butterfly-fat-tree topology, and a special upward network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional symmetric, Manhattan mesh architecture shows that MFPGA can implement circuits with smaller area and better speed

Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter

International audienceThe complexity of circuits to implement on FPGA has necessitated to explore hierarchical interconnect architectures. A large body of work shows that a good partitioning hierarchy, as measured by the associated rent parameter, will correspond to an area-efficient layout. We define the architecture rent parameter of a netlist to be the lowest bound on the rent parameter of any partitioning hierarchy of the netlist. Experimental results show that a combination between a multilevel bottom-up clustering and a top-down refinement generates partitioning hierarchies whose rent parameters are lower than those of other methods

Configuration tools for a new multilevel hierarchical FPGA

International audienceIn this paper we evaluate a new multi-level hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks: A downward network based on the Butterfly-Fat-Tree topology and a special hierarchical upward network. The Downward network uses linear populated and unidirectional Switch Boxes (SBs) and gives one path from each wire-source in the top to reach a leaf (Logic Block: LB) in the lowest level. The upward network connects the LBs output and the input Pads to the SBs situated in different levels of the downward network. New tools are developed to program the new architecture. The global placement approach uses a combination of clustering and partitioning with adaptations to deal with the multi-level interconnect topology. First we run a multi-level bottom-up clustering to reduce external connections. Second we run a multi-level top-down refinement to reduce signals bandwidth of clusters in each level. A detailed placer defines the position of each LB inside a cluster and considers more complex routing constraints. The router is an adaptation of Pathfinder. The global routing consists on selecting the level to use. Signals routing is immediate since path to reach a destination is predictable and unique. Results are based on the MCNC benchmarks and they quantify the LB occupancy and routability. Comparison with the traditional symmetric Manhattan mesh architecture shows that MFPGA can implement circuits with fewer switches and a smaller total area