Design and analysis of Low Power High Speed Pulse Triggered Flip Flop

The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre

Power Theft Identification Using Embedded System

Today, power theft plays the key role in transmission losses of electricity from the generating station to the consumer end. About 30% of power produced is being theft. Though the electricity boards know that there is power theft in the area under their vigilance, they are not able to locate the area or location of theft. So, to identify the power theft and to communicate to the EB there needs a system to be developed. Here comes the system developed by us which will find the power theft if it happens and sends the information about the place of the theft to the nearby Electricity Board