Automatic classification of digital communication modulation schemes

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Digital modulation recognisers based on feed-forward neural networks

Abstract not available

Stochastic computing with spiking neural P systems

This paper presents a new computational framework to address the challenges in deeply scaled technologies by implementing stochastic computing (SC) using the Spiking Neural P (SN P) Systems. SC is well known for its high fault tolerance and its ability to compute complex mathematical operations using minimal amount of resources. However, one of the key issues for SC is data correlation. This computation can be abstracted and elegantly modeled by using SN P systems where the stochastic bit-stream can be generated through the neurons spiking. Furthermore, since SN P systems are not affected by data correlations, this effectively mitigate the accuracy issue in the ordinary SC circuitry. A new stochastic scaled addition realized using SN P systems is reported at the end of this paper. Though the work is still at the early stage of investigation, we believe this study will provide insights to future IC design development.Published versio

LFSR based S-box for lightweight cryptographic implementation

This paper presents the hardware implementation of the Linear Feedback Shift Register (LFSR) based Substitution Box (S-Box) using ALTERA FPGA platform. Unlike the conventional designs, the proposed architecture is low in terms of its hardware cost; the total area and power consumptions. Hence, the new LFSR based S-box can be deployed in block ciphers to achieve lightweight cryptographic implementations

Survey on the applications of artificial neural networks in computer games

Abstract not available

A low complexity multi-line code for cancellable fingerprint template

In this paper, we propose a low computational cost cancelable fingerprint template, namely the multi-line codes. The generation of a line code involves the inspection of minutiae distribution along a straight line constructed based on the reference minutia. Multi-line code is also introduced to elevate the performance of the original single-line code representation. Comprehensive experiments on FVC databases further ascertain that the proposed method yields relatively low computational complexity as compared to existing minutiae distribution-based methods, while preserving the performance. The average equal error rate obtained for stolen-key scenario is 6.69%, and the total arithmetic operations utilized are 14,520 additions and zero multiplication

Compact and short critical path finite field inverter for cryptographic S-box

A substitution box (S-box) plays a crucial role in symmetric key cryptography with block ciphers, such as those found in the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES). It serves as the predominant component in most block ciphers, of which the computational complexity impacts the security of the ciphers directly. In essence, a S-box performs a non-linear transformation of the input data block through a finite field inversion, which is incidentally the most expensive operation in digital computation of finite field arithmetic. Consequently, its computational cost will also increase the overall hardware requirements and in turn, decrease the overall performance of the ciphers. With the emergence of Internet of Things (IoT), the need for highly secured yet lightweight implementation protocols is becoming increasingly more observable. In this paper, we propose a new finite field inverter over GF(28) with a significant area cost saving, achieved through direct computation and followed by algebraic factorization and common sub-expression elimination (CSE). The proposed inverter could be deployed into AES cipher on highly area-constrained digital platform