Advanced Design of High Frequency Analog and Digital Circuits

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3.1-3.6 GHz 22 W GaN Doherty Power Amplifier

This paper presents a Doherty power amplifier working from 3.1 GHz to 3.6 GHz. It adopts 10 W packaged GaN HEMTs from Cree/Wolfspeed and achieves a saturated output power in excess of 43.4 dBm. Saturated efficiency ranges from 57.7 % to 75.2 %, while efficiency at 6 dB back-off is between 44.2 % and 59.8 %. System-level simulations at 3.5 GHz adopting a 16QAM signal with 5 MHz bandwidth and 4 dB peak to average power ratio showed an adjacent channel power ratio of -28 dBc/Hz without pre-distortion, at an average output power of 43 dBm and with an average efficiency of 71 %

A 3-3.8 GHz Class-J GaN HEMT Power Amplifier

This paper presents a wideband class J power amplifier (PA) based on a packaged 10 W GaN HEMT device covering the 3 GHz to 3.8 GHz frequency range. A good trade-off between efficiency and gain has been pursued in synthesizing the second harmonic output termination. The achieved output power is in excess of 41 dBm with drain efficiency ranging from 59 % to 65.5 % and a small signal gain above 14 dB. Preliminary large signal measurements at 3.3 GHz confirm the proper behavior of the PA

Broadband Class-J GaN Doherty Power Amplifier

This paper presents a broadband 3 GHz–3.7GHz class-J Doherty power amplifier exploiting second harmonic tuning in the output network. Furthermore, the output impedance inverter is eliminated and its effect is embedded in the main device’s output matching network, thus trading off among bandwidth, efficiency, and gain. The proposed amplifier adopts two 10W packaged GaN transistors, and it achieves in measurement 60–74%, and 46–50% drain efficiency at saturation and 6 dB output back-off, respectively, with a saturated output power of 43 dBm–44.2dBm and a small-signal gain of 10 dB–13 dB. The proposed DPA exhibits a simulated adjacent channel power ratio less than 30 dBc at 36dBm average output power when a 16-QAM modulation with 5 MHz bandwidth is applied to the 3.5 GHz carrier

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature