Fast and Efficient Light Intensity Modulation in SOI with Gate-All-Around Transistor Phase Modulator

We report fast modulation (>30 GHz) in a SOI resonant cavity using integrated Bragg mirrors and a gate-all-around transistor as active element. Modulation depth >90% can be obtained in 12.5 μm long devices

Prospects for logic-on-a-wire

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced current drive, whereas the body-strapped structures allow for active leakage control and in some cases impact ionization devices. We demonstrate an inverter fabricated along a single silicon rib. The inverter consists of two enhancement mode body-strapped @W-gate NMOS transistors. Static and dynamic experiments demonstrate a fully functional inverter with the output experiencing V"D"D/2 voltage swing, as expected for an NMOS inverter with identical driver and load dimensions. In addition, we propose the use of these devices for cross-bar memory addressing

Reliable Circuit Design with Nanowire Arrays

The emergence of different fabrication techniques of silicon nanowires (SiNWs) raises the question of finding a suitable architectural organization of circuits based on them. Despite the possibility of building conventional CMOS circuits with SiNWs, the ability to arrange them into regular arrays, called crossbars, offers the opportunity to achieve higher integration densities. In such arrays, molecular switches or phase-change materials are grafted at the crosspoints, i.e., the crossing nanowires, in order to perform computation or storage. Given the fact that the technology is not mature, a hybridization of CMOS circuits with nanowire arrays seems to be the most promising approach. This chapter addresses the impact of variability on the nanowires in circuit designs based on the hybrid CMOS-SiNW crossbar approach

Non-hysteretic punchthrough impact ionization MOS (PIMOS) transistor: Application to abrupt inverter and NDR circuits

The recently proposed PIMOS transistor can offer, by appropriate operation, non-hysteretic abrupt off-on transitions due to impact ionization if the action of its parasitic bipolar transistor is minimized. This work proposes non-hysteretic abrupt inverter circuits based on <10 mV/decade room temperature current switching and a tunable negative differential resistance based on punch-through impact ionization MOS transistors (PIMOS) when parasitic bipolar action is cancelled by choosing an appropriate drain voltage. The proposed circuit architectures are compatible with silicon CMOS nodes. The very abrupt non-hysteretic inverter shows gain of the order of -100 in the transition region of the voltage transfer characteristic (VTC). The NDR circuit exhibits tunable peak-to-valley PVR values and a negative resistance in the range of hundreds of kOmega

Abrupt NMOS Inverter Based on Punch-Through Impact Ionization With Hysteresis in the Voltage Transfer Characteristics

In this letter, an abrupt NMOS inverter based on punch-through impact ionization is demonstrated for the first time. The slopes for both the rising and the falling edge of the ID(V GS) device characteristics are less than 10 mV/decade steep which translates into a gain of -80 for the inverter. In addition, the voltage transfer characteristic shows a hysteresis whose width depends on the biasing. The output swing is approximately twice the input voltage swing, which assures proper cascadability of logic gates

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching (3-10 mV/dec.) as well as hysteresis in both $I_D(V_{DS})$ and $I_D(V_{GS})$. An inverter gain as high as -80 and a 300 mV hysteresis width in the transfer characteristics are reported at room temperature. Temperature stability of the devices up to 125degC and operation for more than $10^4$ cycles without significant degradation are demonstrated, much beyond the performances of previously reported I-MOS device

The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs

Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm2 /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform