Sensitivity to Anilinopyrimidines and Phenylpyrroles in «Botrytis cinerea» in North-Italian Vineyards

Several commercial vineyards, located in Piedmont (Northern Italy), were monitored in order to evaluate the sensitivity of Botrytis cinerea Pers., the causal agent of grey mould, to five classes of botryticides: benzimidazoles, dicarboximides, phenylcarbamates, anilinopyrimidines and phenylpyrroles. Strains of B. cinerea resistant to anilinopyrimidines were easily detected, particularly in 1999, a year characterized by high disease pressure, even in vineyards not sprayed with that class of fungicides. Fludioxonil-resistance, on the contrary, was not detected. Resistance to benzimidazoles and dicarboximides was at previous observed levels. For the first time, resistance to phenylcarbamates was detected in the field. Strains of B. cinerea showing multiple resistance to benzimidazoles, dicarboximides and anilinopyrimidines and maintaining a good level of virulence, as shown by tests carried out on wounded apples, are present in Italian vineyards. Strategies in the use of the botryticides are discussed, in order to avoid a loss of disease control

RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology

The 2008 Corona effort was inspired by a pressing need for more of everything, as demanded by the salient problems of the day. Dennard scaling was no longer in effect. A lot of computer architecture research was in the doldrums. Papers often showed incremental subsystem performance improvements, but at incommensurate cost and complexity. The many-core era was moving rapidly, and the approach with many simpler cores was at odds with the better and more complex subsystem publications of the day. Core counts were doubling every 18 months, while per-pin bandwidth was expected to double, at best, over the next decade. Memory bandwidth and capacity had to increase to keep pace with ever more powerful multi-core processors. With increasing core counts per die, inter-core communication bandwidth and latency became more important. At the same time, the area and power of electrical networks-on-chip were increasingly problematic: To be reliably received, any signal that traverses a wire spanning a full reticle-sized die would need significant equalization, re-timing, and multiple clock cycles. This additional time, area, and power was the crux of the concern, and things looked to get worse in the future. Silicon nanophotonics was of particular interest and seemed to be improving rapidly. This led us to consider taking advantage of 3D packaging, where one die in the 3D stack would be a photonic network layer. Our focus was on a system that could be built about a decade out. Thus, we tried to predict how the technologies and the system performance requirements would converge in about 2018. Corona was the result this exercise; now, 15 years later, it's interesting to look back at the effort.Comment: 2 pages. Proceedings of ISCA-50: 50 years of the International Symposia on Computer Architecture (selected papers) June 17-21 Orlando, Florid

The combined perceptron branch predictor.

Abstract. Previous works have shown that neural branch prediction techniques achieve far lower misprediction rate than traditional approaches. We propose a neural predictor based on two perceptron networks: the Combined Perceptron Branch Predictor. The predictor consists of two concurrent perceptron-like neural networks, one using as inputs branch history information, the other one using program counter bits. We carried out experiments proving that this approach provides lower misprediction rate than state-of-the-art conventional and neural predictors. In particular, when compared with an advanced path-based perceptron predictor, it features 12% improvement of the prediction accuracy

A.: Power/performance/thermal design-space exploration for multicore architectures

Abstract—Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better thermal/power scaling (many small cores dissipate less than a large and complex one), and the ease and reuse of design. This paper presents a thorough evaluation of multicore architectures. The architecture that we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1, shared/private L2, and a shared bus interconnect. We consider a benchmark set composed of several parallel shared memory applications. We explore the design space related to the number of cores, L2 cache size, and processor complexity, showing the behavior of the different configurations/applications with respect to performance, energy consumption, and temperature. Design trade-offs are analyzed, stressing the interdependency of the metrics and design factors. In particular, we evaluate several chip floorplans. Their power/thermal characteristics are analyzed, showing the importance of considering thermal effects at the architectural level to achieve the best design choice. Index Terms—Chip multiprocessor, design-space exploration, thermal-aware microarchitectures, power/performance. Ç