Energy-efficient and High-bandwidth Density Monolithic Optical Transceivers in Advanced CMOS Processes

Today's conventional cloud computing and mobile platforms have been challenged by the advent of Machine Learning (ML) and Internet of Things (IoT). The performance and diversity requirements of these applications demand the shift towards hyper-scale data centers, Exascale high-performance computing (HPC), energy-efficient edge computing, and new sensing and imaging modalities. My research goal is to design and implement large-scale and energy-efficient integrated systems that answer these technological changes by merging state-of-the-art electronics with photonics. This thesis developes several monolithic photonics platforms in advanced CMOS technologies that were designed as key enablers for the next-generation of integrated systems: (1) Using unmodified CMOS in 32/45nm SOI nodes places photonics next to one of the fastest transistors and enhances integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without the complications of 3D integration approaches. (2) Poly-silicon based photonics in bulk CMOS as a path for embedding photonics in the most advanced CMOS nodes (sub-10nm). We demonstrate system results using these platforms for the immediate application area of high-performance optical transceivers. We elaborate on the electronic-photonic co-optimization opportunities on the example of optical interconnect application, a 40Gb/s optical transmitter achieving the world record energy and bandwidth density. Furthermore, we explain how deep insight into details of an advanced CMOS process can leverage photonic device design, enabling new degrees of freedom in a seemingly constrained environment. Lastly, we demonstrate the first monolithic integrated photonics platform in a commercial 300mm-wafer bulk CMOS technology. We implemented the photonic system-on-chip (SoC) in this platform for in-situ device characterization and process development, and demonstrated wavelength division multiplexed (WDM) optical transceivers. These integrated platforms and system design methodologies can unlock new functionalities in many applications such as HPC, high-bandwidth wireless connectivity, LiDAR, bio-sensing, etc

Generalisation of code division multiple access systems and derivation of new bounds for the sum capacity

In this study, the authors explore a generalised scheme for the synchronous code division multiple access (CDMA). In this scheme, unlike the standard CDMA systems, each user has different codewords for communicating different messages. Two main problems are investigated. The first problem concerns whether uniquely detectable overloaded matrices (an injective matrix, i.e. the inputs and outputs are in one-to-one correspondence depending on the input alphabets) exist in the absence of additive noise, and if so, whether there are any practical optimum detectors for such input codewords. The second problem is about finding tight bounds for the sum channel capacity. In response to the first problem, the authors have constructed uniquely detectable matrices for the generalised scheme and the authors have developed practical maximum likelihood detection algorithms for such codes. In response to the second problem, lower bounds and conjectured upper bounds are derived. The results of this study are superior to other standard overloaded CDMA codes since the generalisation can support more users than the previous schemes

Fully Integrated Time-Gated 3D Fluorescence Imager for Deep Neural Imaging

This paper presents a device for time-gated fluorescence imaging in the deep brain, consisting of two on-chip laser diodes and 512 single-photon avalanche diodes (SPADs). The edge-emitting laser diodes deliver fluorescence excitation above the SPAD array, parallel to the imager. In the time domain, laser diode illumination is pulsed and the SPAD is time-gated, allowing a fluorescence excitation rejection up to O.D. 3 at 1 ns of time-gate delay. Each SPAD pixel is masked with Talbot gratings to enable the mapping of 2D array photon counts into a 3D image. The 3D image achieves a resolution of 40, 35, and 73 μm in the x, y, and z directions, respectively, in a noiseless environment, with a maximum frame rate of 50 kilo-frames-per-second. We present measurement results of the spatial and temporal profiles of the dual-pulsed laser diode illumination and of the photon detection characteristics of the SPAD array. Finally, we show the imager's ability to resolve a glass micropipette filled with red fluorescent microspheres. The system's 420 μm-wide cross section allows it to be inserted at arbitrary depths of the brain while achieving a field of view four times larger than fiber endoscopes of equal diameter

Fully Integrated Time-Gated 3D Fluorescence Imager for Deep Neural Imaging

This paper presents a device for time-gated fluorescence imaging in the deep brain, consisting of two on-chip laser diodes and 512 single-photon avalanche diodes (SPADs). The edge-emitting laser diodes deliver fluorescence excitation above the SPAD array, parallel to the imager. In the time domain, laser diode illumination is pulsed and the SPAD is time-gated, allowing a fluorescence excitation rejection up to O.D. 3 at 1 ns of time-gate delay. Each SPAD pixel is masked with Talbot gratings to enable the mapping of 2D array photon counts into a 3D image. The 3D image achieves a resolution of 40, 35, and 73 μm in the x, y, and z directions, respectively, in a noiseless environment, with a maximum frame rate of 50 kilo-frames-per-second. We present measurement results of the spatial and temporal profiles of the dual-pulsed laser diode illumination and of the photon detection characteristics of the SPAD array. Finally, we show the imager's ability to resolve a glass micropipette filled with red fluorescent microspheres. The system's 420 μm-wide cross section allows it to be inserted at arbitrary depths of the brain while achieving a field of view four times larger than fiber endoscopes of equal diameter

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics