A comparative study of defect energy distribution and its impact on degradation kinetics in GeO2/Ge and SiON/Si pMOSFETs

High mobility germanium (Ge) channel is considered as a strong candidate for replacing the Si in pMOSFETs in near future. It has been reported that the conventional power-law degradation kinetics of Si devices is inapplicable to Ge. In this work, further investigation is carried out on defect energy distribution, which clearly shows that this is because the defects in GeO2/Ge and SiON/Si devices have different physical properties. Three main differences are: 1) Energy alternating defects (EAD) exist in Ge devices but insignificant in Si; 2) The distribution of as-grown hole traps (AHT) has a tail in the Ge band gap but not in Si, which plays an important role in degradation kinetics and device lifetime prediction; 3) EAD generation in Ge devices requires the injected charge carriers to overcome a 2nd energy barrier, but not in Si. Taking the above differences into account, the power law kinetics of EAD generation can be successfully restored by following a new procedure, which can assist in the Ge process/device optimization

NBTI of Ge pMOSFETs: understanding defects and enabling lifetime prediction

Ge pMOSFETs are strong candidates for next technology nodes and record hole mobility has been reported for Al2O3/GeO2/Ge and HfO2/SiO2/Si-cap/Ge structures. Reliability, however, is still problematic and currently impedes the progress. Large NBTI exists in GeO2/Ge, and little is known about the defects. Si-cap/Ge device has superior reliability, but its lifetime, τ, cannot be predicted by power law extrapolation. This work demonstrates that the defects are different in Ge and Si devices. For the first time, a method is developed for Ge devices to restore the power law for NBTI kinetics, which enables τ prediction and process optimization

AC NBTI of Ge pMOSFETs: Impact of Energy Alternating Defects on Lifetime Prediction

For the first time, AC lifetime in Si-cap/Ge and GeO2/Ge pMOSFETs is investigated and it must not be predicted by the conventional DC stress method with a measurement delay. This is because the energy alternating defects are generated in Ge devices but not in Si, which introduces additional generation under DC stress

Energy Distribution of Positive Charges in Al2O3/GeO2/Ge pMOSFETs

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3-GeO2-Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3/GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3/GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With GeO2/Al2O3 Stack

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the timeexponent varies with stress biases/field when measured by either the conventional slow dc or pulse I–V technique, making the conventional Vg-accelerated method for predicting the lifetime of Si pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 °C; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev, when neutral, lift well above Ev after charging, and return below Ev following neutralization

Low-frequency noise characterization of strained germanium pMOSFETs

Low-frequency noise in strained Ge epitaxial layers, which are grown on a reverse-graded relaxed SiGe buffer layer, has been evaluated for different front-end processing conditions. It has been shown that the 1/f noise in strong inversion is governed by trapping in the gate oxide (number fluctuations) and not affected by the presence of compressive strain in the channel. However, some impact has been found from the type of halo implantation used, whereby the lowest noise spectral density and the highest hole mobility are obtained by replacing the standard As halo by P implantation. At the same time, omitting the junction anneal results in poor device characteristics, which can be understood by considering the presence of a high density of nonannealed implantation damage in the channel and the gate stack near the source and the drain

Lyre et pinceau, ou Jésus Dieu des arts : esquisses poétiques et morales d'après l'Évangile / par M. l'abbé Mitard

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"Y function" method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction

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