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    Novel Multi-layer Wiring Build-up using Electrochemical Pattern Replication (ECPR)

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    Abstract This paper discloses a novel, high accuracy and low cost integration method based on an Electrochemcial Pattern Replication (ECPR) technology for multi-level stacking applications such as integrated passives, multi-level redistribution layers and top level IC interconnect structures. It is demonstrated how a first copper layer is coated with BCB (Bisbenzocyclobutene), which is planarized with CMP (Chemical Mechanical Polishing) to uncover the first layer, where after a second patterned copper layer is fabricated with ECPR. This approach shows the feasibility of fabricating highly accurate multi-level wiring layers and still avoiding the issues related to increasing topography, which are particularly severe for thick metal layers. In addition, the constraints for the dielectric material is significantly reduced, since it does not have to be photosensitive or planarizing, which in turn opens up for the use of alternative dielectric materials, which may have better electrical and physical properties, that have not been usable with the traditional multi-level fabrication methods. Introduction The integration of more and more complex functions such as wireless communication capabilities on chips or packages puts new demands on the manufacturing methods for top metal layers. High density interconnects and integrated passives require a combination of resolution, accuracy, thickness uniformity typically offered only by dual damascene processes. At the same time there is a need for thicker metal, high deposition rates and low cost per layer, which is typically offered only by through mask plating processes. These combined requirements are difficult to address by most existing methods of today. The increasing demand for further miniaturization and functionality for electronic systems, particularly for mobile and wireless applications, has been driving the trend of fabricating multi-layer wiring, such as integrated passives and redistribution layers for Wafer Level Packaging (WLP) applications Particular for above-IC integrated passives and Integrated passive devices (IPDs) there has been a trend of fabricating thicker metal (copper circuits) since it lowers the series resistance of the devices, which in turn results in better performance (e.g higher capacitance or inductance value per area
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