147 research outputs found

    Profile Guided Dataflow Transformation for FPGAs and CPUs

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    This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation

    RIPL: An Efficient Image Processing DSL for FPGAs

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    Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting fine-grained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL, an image processing domain specific language (DSL) for FPGAs. It has algorithmic skeletons to express image processing, and these are exploited to generate deep pipelines of highly concurrent and memory-efficient image processing components.Comment: Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320

    Power efficient dataflow design for a heterogeneous smart camera architecture

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    Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low

    Mitigating sampling error when measuring internet client IPv6 capabilities

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    Despite the predicted exhaustion of unallocated IPv4 addresses be- tween 2012 and 2014, it remains unclear how many current clients can use its successor, IPv6, to access the Internet. We propose a refinement of previous measurement studies that mitigates intrin- sic measurement biases, and demonstrate a novel web-based tech- nique using Google ads to perform IPv6 capability testing on a wider range of clients. After applying our sampling error reduction, we find that 6% of world-wide connections are from IPv6-capable clients, but only 1–2% of connections preferred IPv6 in dual-stack (dual-stack failure rates less than 1%). Except for an uptick around IPv6-day 2011 these proportions were relatively constant, while the percentage of connections with IPv6-capable DNS resolvers has in- creased to nearly 60%. The percentage of connections from clients with native IPv6 using happy eyeballs has risen to over 20

    Profile driven dataflow optimisation of mean shift visual tracking

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    Profile guided optimisation is a common technique used by compilers and runtime systems to shorten execution runtimes and to optimise locality aware scheduling and memory access on heterogeneous hardware platforms. Some profiling tools trace the execution of low level code, whilst others are designed for abstract models of computation to provide rich domain-specific context in profiling reports. We have implemented mean shift, a computer vision tracking algorithm, in the RVC-CAL dataflow language and use both dynamic runtime and static dataflow profiling mechanisms to identify and eliminate bottlenecks in our naive initial version. We use these profiling reports to tune the CPU scheduler reducing runtime by 88%, and to optimise our dataflow implementation that reduces runtime by a further 43% - an overall runtime reduction of 93%. We also assess the portability of our mean shift optimisations by trading off CPU runtime against resource utilisation on FPGAs. Applying all dataflow optimisations reduces FPGA design space significantly, requiring fewer slice LUTs and less block memory

    'Moments of Change' as opportunities for influencing behaviour

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    This document is the final report from Project EV0506 – “Moments of change” as opportunities for influencing behaviour. It was commissioned by the Centre of Expertise on Influencing Behaviours at the Department of Environment, Food and Rural Affairs (Defra). The goal of the project was to explore whether “moments of change” – times in a person‟s life where existing habits and behavioural patterns are disrupted – provide a significant opportunity to encourage the take-up of pro-environmental behaviours. In particular, the project focused on life events (such as having a baby) and macroeconomic events (such as the 2008/9 “credit crunch”)

    14-3-3 Proteins Interact with a Hybrid Prenyl-Phosphorylation Motif to Inhibit G Proteins

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    Signaling through G proteins normally involves conformational switching between GTP- and GDP-bound states. Several Rho GTPases are also regulated by RhoGDI binding and sequestering in the cytosol. Rnd proteins are atypical constitutively GTP-bound Rho proteins, whose regulation remains elusive. Here, we report a high-affinity 14-3-3-binding site at the C terminus of Rnd3 consisting of both the Cys241-farnesyl moiety and a Rho-associated coiled coil containing protein kinase (ROCK)-dependent Ser240 phosphorylation site. 14-3-3 binding to Rnd3 also involves phosphorylation of Ser218 by ROCK and/or Ser210 by protein kinase C (PKC). The crystal structure of a phosphorylated, farnesylated Rnd3 peptide with 14-3-3 reveals a hydrophobic groove in 14-3-3 proteins accommodating the farnesyl moiety. Functionally, 14-3-3 inhibits Rnd3-induced cell rounding by translocating it from the plasma membrane to the cytosol. Rnd1, Rnd2, and geranylgeranylated Rap1A interact similarly with 14-3-3. In contrast to the canonical GTP/GDP switch that regulates most Ras superfamily members, our results reveal an unprecedented mechanism for G protein inhibition by 14-3-3 proteins
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