Validation and test-retest repeatability performance of parametric methods for [11C]UCB-J PET

[(11)C]UCB-J is a PET radioligand that binds to the presynaptic vesicle glycoprotein 2A. Therefore, [(11)C]UCB-J PET may serve as an in vivo marker of synaptic integrity. The main objective of this study was to evaluate the quantitative accuracy and the 28-day test–retest repeatability (TRT) of various parametric quantitative methods for dynamic [(11)C]UCB-J studies in Alzheimer’s disease (AD) patients and healthy controls (HC). Eight HCs and seven AD patients underwent two 60-min dynamic [(11)C]UCB-J PET scans with arterial sampling over a 28-day interval. Several plasma-input based and reference-region based parametric methods were used to generate parametric images using metabolite corrected plasma activity as input function or white matter semi-ovale as reference region. Different parametric outcomes were compared regionally with corresponding non-linear regression (NLR) estimates. Furthermore, the 28-day TRT was assessed for all parametric methods. Spectral analysis (SA) and Logan graphical analysis showed high correlations with NLR estimates. Receptor parametric mapping (RPM) and simplified reference tissue model 2 (SRTM2) BP(ND), and reference Logan (RLogan) distribution volume ratio (DVR) regional estimates correlated well with plasma-input derived DVR and SRTM BP(ND). Among the multilinear reference tissue model (MRTM) methods, MRTM1 had the best correspondence with DVR and SRTM BP(ND). Among the parametric methods evaluated, spectral analysis (SA) and SRTM2 were the best plasma-input and reference tissue methods, respectively, to obtain quantitatively accurate and repeatable parametric images for dynamic [(11)C]UCB-J PET. SUPPLEMENTARY INFORMATION: The online version contains supplementary material available at 10.1186/s13550-021-00874-8

A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains

Abstract—A robust, scalable, and power efficient dual-clock first-input first-out (FIFO) architecture which is useful for transferring data between modules operating in different clock domains is presented. The architecture supports correct operation in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer; and with arbitrary clock frequency changes, halting, and restarting in either or both clock domains. The architecture is demonstrated in both a 0.18- m CMOS full-custom design and a 0.18- m CMOS standard cell design used in a globally asynchronous locally synchronous array processor. It achieves 580-MHz operation and 10.3-mW power dissipation while performing simultaneous FIF

A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links

Primary healthcare and the battle against childhood physical inactivity and obesity

The physical activity pandemic is of particular concern with regard to children. Catherine Elliot of Lincoln University, New Zealand, Lee Stoner of Massey University, New Zealand, Michael Hamlin of Lincoln University and Mark Stoutenberg of the University of Miami, USA, consider the role of primary healthcare in the fight against childhood physical inactivity and obesity