Atomistic Approach to Alloy Scattering in Si(1-x)Ge(x)

SiGe alloy scattering is of significant importance with the introduction of strained layers and SiGe channels into complementary metal-oxide semiconductor technology. However, alloy scattering has till now been treated in an empirical fashion with a fitting parameter. We present a theoretical model within the atomistic tight-binding representation for treating alloy scattering in SiGe. This approach puts the scattering model on a solid atomistic footing with physical insights. The approach is shown to inherently capture the bulk alloy scattering potential parameters for both n-type and p-typecarriers and matches experimental mobility data

Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.Comment: 9 pages, 4 figures, *G.C.T. and A.P. contributed equally to this wor

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.Comment: 12 figures, 13 pages, Submitted to Journal of Applied Physic

Observation of 1D Behavior in Si Nanowires: Toward High-Performance TFETs

This article provides experimental evidence of one-dimensional behavior of silicon (Si) nanowires (NWs) at low-temperature through both transfer (Id−VG) and capaci- tance−voltage characteristics. For the first time, operation of Si NWs in the quantum capacitance limit (QCL) is experimentally demonstrated and quantitatively analyzed. This is of relevance since working in the QCL may allow, e.g., tunneling field-effect transistors (TFETs) to achieve higher on-state currents (Ion) and larger on-/off-state current ratios (Ion/Ioff), thus addressing one of the most severe limitations of TFETs. Comparison of the experimental data with simulations finds excellent agreement using a simple capacitor model

Physics and simulation study of nanoscale electronic devices

Silicon based CMOS technology has seen continuous scaling of device dimensions for past three decades. There is a lot of focus on incorporating different high mobility channel materials and new device architectures for post-Si CMOS logic technology, making it a multifaceted problem. In this thesis some of the multiple challenges concerning new CMOS technologies are addressed. High carrier mobility alloyed channel materials like SiGe and InGaAs suffer from scattering due to disorder called, alloy scattering. The current theory of alloy scattering present in literature/text books can be called rudimentary at the best due to lack of a strong theoretical foundation and/or use of fitting parameters to explain experimental measurements. We present a new atomistic approach based on tight-binding parameters to understanding the alloy disorder. Using this approach we are able to provide new insights into the theory of alloy scattering and explain the experimental measurements in bulk SiGe and InGaAs that were till now based on just fitting parameters. With an updated understanding of alloy scattering, hole mobility in SiGe nanowires is calculated using a linearized Boltzmann formalism. Bulk Ge exhibits high hole mobility makeing it ideal for PMOS devices. Nano patterning of Ge/SiGe leads to Ge nanofins with both uniaxial and biaxial strain components, making it a device architecture design problem. Fully atomistic simulations involving molecular dynamics (ReaxFF force field) based relaxation for strain relaxation; tight-binding based bandstructure calculations and a linearized Boltzmann transport model for mobility calculations are performed. Final phonon mobility calculations reveal nearly 3.5 X improvements compared to biaxial strained Ge in Ge nanofins with width reduction. High electron mobility III--V\u27s are projected to be a material of choice for post-Si NMOS. These low electron mass materials suffer from the \u27DOS bottleneck\u27 issue. Transistor designs based on using mixed Gamma-L valleys for electron transport are proposed to overcome the density of states (DOS) bottleneck. Improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-Insulator-based single gate thin-body n-channel transistors. Finally, a critical question that has to do with scaling is - How small a useful MOS transistor can be? As transistor channel lengths are scaled to lengths shorter than Lg \u3c 8 nm, direct source-drain tunneling starts to limit the transistor operation. Scaling approaches needed in this tunneling dominated regime are discussed using atomistic quantum mechanical simulations

Atomistic Simulations for SiGe pMOS Devices - Bandstructure to Transport

SiGe pMOSFETs show considerable improvements in device performance due to the smaller hole effective mass exhibited by Ge.Further improvement in device performance can be obtained by growing pseudomorphically compressively strained SiGe on Si. Despite a lattice mismatch of ~4% between Si and Ge, researchers have been recently able to fabricate ultrathin body and nanowire pMOSFETs with high Ge concentrations and compressive strain [1,2]. Strained SiGe pMOS devices are being considered as one of the designs for the ultimate pMOS [3]. To treat quantum confined devices atomistic modeling becomes important. Here we present tight-binding (TB) based bandstructure calculations in the virtual crystal approximation (VCA) for bulk relaxed SiGe and strained SiGe on (100) Si benchmarked against experimental data

Simulation Study of Thin-Body Ballistic n-MOSFETs Involving Transport in Mixed Gamma-L Valleys

Transistor designs based on using mixed Gamma-L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (tau) due to its single Gamma valley