115 research outputs found

    A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths

    Get PDF

    A Thread Partitioning Algorithm in Low Power High-Level Synthesis

    Get PDF

    Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning

    Get PDF

    FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction

    Get PDF

    Instruction Set and Functional Unit Synthesis for SIMD Processor Cores

    Get PDF

    A Reconfigurable Adaptive FEC System for Reliable Wireless Communications

    Get PDF

    An Efficient Algorithm/Architecture Codesign for Image Encoders

    Get PDF

    A hardware/software partitioning algorithm for SIMD processor cores

    Get PDF
    corecore