Creating options for 3D-SIC testing

Three-dimensional stacked ICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all of the above can only become true if 3D-SICs can be properly tested for manufacturing defects. Companies have started to develop their test strategies for these products, and the outcome is largely dependent on (1) the necessity of test generation for specific new 3D defects, (2) the feasibility of access the test targets, and (3) the economic trade-offs involved. Test research is needed to create options for these challenges

Microelectronics and test in The New Europe - challenges and opportunities in research and industry

An evening panel session entitled Microelectronics and Test in 'The New Europe'--Challenges and Opportunities in Research and Industry, took place on 23 May at the 10th European Test Symposium (ETS 05). Raimund Ubar and Hans-Joachim Wunderlich (University of Stuttgart) organized the panel session, and Erik Jan Marinissen (Philips Research) served as moderator. Panelists included representatives of the Eastern European countries that have recently joined the EU, those who live and work outside the EU, and Western companies with branches or subcontractors in Eastern European countries.A panel session at the 3rd IEEE Infrastructure IP (IIP) Workshop held in conjunction with the VLSI Test Symposium focused on the question, Is silicon debug the Cinderella of infrastructure IP? IEEE Design & Test coorganized the panel session, and R. Chandramouli of Virage Logic served as chair

3D test: no longer a bottleneck!

When I joined imec in October 2008 to work on test and design-for-test (DfT) of 3D-stacked integrated circuits (ICs), there were only a few test folks active in that emerging field. Consequently, misconceptions about 3D test were omni-present. In the November 18, 2008 issue of Semiconductor International, Alexander Braun wrote: “At a symposium yesterday on 3-D integration, leading expert Philip Garrou detailed the rise of the technology as well as the challenges facing it, including test, yield, and design. (…) Test, again, will be a significant problem. Memory can be stacked as known good die, because the memory chips can be tested, but years from now, as different functions are pulled apart to stack them, there is no clear way to test them because they do not form a complete circuit. This will hold up things like the full partitioning of chips.”1 3D InCites’ tenth anniversary is a good occasion to report on the state of 3D testing and publicly declare that it's no longer a bottleneck for 3D integration

Security versus test quality: can we only have one at a time?

part of ITC 2004 panels: Part

Creating options for 3D-SIC testing

Three-dimensional stacked ICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all of the above can only become true if 3D-SICs can be properly tested for manufacturing defects. Companies have started to develop their test strategies for these products, and the outcome is largely dependent on (1) the necessity of test generation for specific new 3D defects, (2) the feasibility of access the test targets, and (3) the economic trade-offs involved. Test research is needed to create options for these challenges

Bugs, moths, grasshoppers, and whales

Popular wisdom has it that the term debug dates back to 1947, when a team working on the Harvard University Mark II Aiken Relay Calculator removed a moth trapped between one of the relays. The team affixed the moth in their log book, and wrote next to it: First actual case of bug being found. The hardware equivalent of software bugs are design errors. Next to those, microelectronics suffers from manufacturing defects. The hardware community uses the term debug for locating and resolving design errors, and uses the term diagnosis for pinpointing the cause and location of manufacturing defects. But is debug really the best term to use? A bug is small and perhaps hard to find, but once located it is easy for a human to defeat. However, some design errors have consequences of giant proportions. Perhaps a better term would be dewhale

Challenges in testing core-based system ICs

Advances in semiconductor design and manufacturing technology enable the design of complete systems on one IC. To develop these system ICs in a timely manner, traditional IC design in which everything is designed from scratch, is replaced by a design style based on embedding large reusable modules, the so-called cores. Effectively, the design of a core-based IC is partitioned over the core provider(s) and the system-chip integrator. The development of tests should follow the same partitioning. We describe the differences between traditional and core-based test development, and present an overview of current industrial approaches. We list the future challenges regarding standardization, tool development, and academic and industrial research

Guest Editors' introduction: the status of IEEE Std 1500

The increased use of embedded predesigned reusable cores necessitates a core-based test strategy. The goal of IEEE Std 1500-2005 is to simplify reuse and facilitate interoperability for testing core-based system chips, especially if they contain cores from different sources. This special issue updates readers on the status of the usage and adoption of this standar

Guest editors' introduction: addressing the challenges of debug and diagnosis

The cost of silicon debug can be considerable and unpredictable. Problems can range from catastrophic to subtle. Once errors have been observed, debug takes over. When problems arise, the first challenge is to categorize them. Causes can range from incorrect specifications to silicon defects, to measurement errors. This special issue focuses on all aspects of a successful debug process: how to prepare, what to do during debug, and how to use the results to improve things in the future. The seven articles in this issue cover a broad variety of topics in silicon debug and diagnosis, as well as the newly emerging middle ground between the two: at-speed timing failures

The role of test protocols in testing embedded-core-based system ICs

\u3cp\u3eA core-based design style introduces new test challenges, which, if not dealt with properly, might defeat the entire purpose of using pre-designed cores. Macro Test is a liberal test approach for core-based designs, i.e., it supports all kinds of test access mechanisms to the embedded cores. The separation of tests into test protocols and test patterns plays a crucial role in Macro Test. Tasks as expansion of core-level tests to chip level, scheduling of tests, and test assembly are carried out on test protocols by software tools. This paper addresses the role of test protocols and features an example of a small scan-Testable core. We argue that the fact that expansion and scheduling take place on test protocols rather than on complete tests is important to reduce the computational complexity of the associated software tools.\u3c/p\u3