Electrical conductivity of parylene F at high temperature

The electrical conductivity of both as-deposited and annealed poly(α,α,α′,α′-tetrafluoro-p-xylylene) (PA-F) films has been investigated up to 400°C. The static conductivity (σ DC) values of PA-F measured between 200°C and 340°C appear to be ∼2.5 orders of magnitude lower for annealed films than for as-deposited ones. This change is attributed to a strong increase in the crystallinity of the material occurring above 340°C. After annealing at 400°C in N2, the σ DC value measured at 300°C, for instance, decreased from 3.8 × 10−12 Ω−1 cm−1 to 7.5 × 10−15 Ω−1 cm−1. Physical interpretations of such an improvement are offered

Real-time crystallization in fluorinated parylene probed by conductivity spectra

Dielectric relaxation spectroscopy experiments were performed at high temperature on fluorinated parylene films during the occurrence of the isothermal crystalline phase transition. For this polymer, since the difference between the glass transition temperature (Tg ) and the phase transition temperature (Tc ) is very strong (Tc  ≥ 4Tg ), segmental and dipolar relaxation usually used to probe the crystallization are not shown in the experiment frequency window (10−1 to 106 Hz) during the crystallization. The charge diffusion becomes the only electrical marker that allows probing the phase transition. During the transition phase, a continuous decrease of about two orders of magnitude is observed in the conductivity values below an offset frequency (fc ) with a tendency to stabilization after 600 min. Below the offset frequency, the decrease of the normalized conductivity to the initial value as function of time is frequency independent. The same behavior is also observed for the fc values that decrease from 160 Hz to about 20 Hz. Above the offset frequency, the electronic hopping mechanism is also affected by the phase transition and the power law exponent (n) of the AC conductivity shows a variation from 0.7 to 0.95 during the first 600 min that tend to stabilize thereafter. Accordingly, three parameters (n, fc , and AC conductivity values for frequencies below f c) extracted from the AC conductivity spectra in different frequency windows seem suitable to probe the crystalline phase transition

Dielectric strength of parylene HT

The dielectric strength of parylene HT (PA-HT) films was studied at room temperature in a wide thickness range from 500 nm to 50 μm and was correlated with nano- and microstructure analyses. X-ray diffraction and polarized optical microscopy have revealed an enhancement of crystallization and spherulites development, respectively, with increasing the material thickness (d). Moreover, a critical thickness dC (between 5 and 10 μm) is identified corresponding to the beginning of spherulite developments in the films. Two distinct behaviors of the dielectric strength (FB ) appear in the thickness range. For d ≥ dC , PA-HT films exhibit a decrease in the breakdown field following a negative slope (FB  ∼ d −0.4), while for d < dC , it increases with increasing the thickness (FB  ∼ d 0.3). An optimal thickness doptim  ∼ 5 μm corresponding to a maximum dielectric strength (FB  ∼ 10 MV/cm) is obtained. A model of spherulite development in PA-HT films with increasing the thickness is proposed. The decrease in FB above dC is explained by the spherulites development, whereas its increase below dC is induced by the crystallites growth. An annealing of the material shows both an enhancement of FB and an increase of the crystallites and spherulites dimensions, whatever the thickness. The breakdown field becomes thickness-independent below dC showing a strong influence of the nano-scale structural parameters. On the contrary, both nano- and micro-scale structural parameters appear as influent on FB for d ≥ dC

Improved Annealing Process for 6H-SiC p⁺-n Junction Creation by Al Implantation

International audienceFive-fold Al implantations at both room temperature and 300°C ranging from 25 keV to 300 keV and a total fluence of 1.75x10 15 cm-2 , have been performed in 6H-SiC epilayers to create p +-n junctions. The samples have been annealed at 1700°C during 30 mn in an inductively heated furnace especially configured. Surface effects, recrystallization, dopant distribution and electrical activation are investigated by XPS, RBS, SIMS and sheet resistance measurements. For both RT and 300°C-implanted samples, good recrystallization and surface stoichiometry are found as well as no dopant loosing and an interesting electrical activation (46% and 99%, respectively). Introduction p +-n junctions in SiC power devices must be realized by ion implantation due to very low diffusion coefficients of dopants in silicon carbide. SiC high density and its structural crystallinity involve a delicate post-implantation annealing. The implantation temperature, annealing environment, time and temperature of annealing and the heating rate are the essential parameters to reorder the crystal damage induced by ion implantation and to activate the dopants by migrating in SiC atomic sites. Initially, after ion implantation, almost all Al dopants are distributed in interstitial sites, where they are not electrically active. We utilized a JIPELEC TM rf induction furnace. This technique of annealing has significant advantages such as the very high rising slope in temperature and the very localized zone of heating (the susceptor). But this one implies high temperature variations, vertically in the enclosure and laterally on the surface of the SiC wafers. These temperature gradients may cause an etching of, or a layer deposition on the SiC surface. Moreover, Si is known to volatilize towards 1400°C at one atmosphere pressure, and in lack of a Si supersaturating vapor the carbonization of the surface is inevitable. This paper presents the results of an optimized thermal rf annealing, which avoids these problems

Improved Annealing Process for 6H-SiC p⁺-n Junction Creation by Al Implantation

International audienceFive-fold Al implantations at both room temperature and 300°C ranging from 25 keV to 300 keV and a total fluence of 1.75x10 15 cm-2 , have been performed in 6H-SiC epilayers to create p +-n junctions. The samples have been annealed at 1700°C during 30 mn in an inductively heated furnace especially configured. Surface effects, recrystallization, dopant distribution and electrical activation are investigated by XPS, RBS, SIMS and sheet resistance measurements. For both RT and 300°C-implanted samples, good recrystallization and surface stoichiometry are found as well as no dopant loosing and an interesting electrical activation (46% and 99%, respectively). Introduction p +-n junctions in SiC power devices must be realized by ion implantation due to very low diffusion coefficients of dopants in silicon carbide. SiC high density and its structural crystallinity involve a delicate post-implantation annealing. The implantation temperature, annealing environment, time and temperature of annealing and the heating rate are the essential parameters to reorder the crystal damage induced by ion implantation and to activate the dopants by migrating in SiC atomic sites. Initially, after ion implantation, almost all Al dopants are distributed in interstitial sites, where they are not electrically active. We utilized a JIPELEC TM rf induction furnace. This technique of annealing has significant advantages such as the very high rising slope in temperature and the very localized zone of heating (the susceptor). But this one implies high temperature variations, vertically in the enclosure and laterally on the surface of the SiC wafers. These temperature gradients may cause an etching of, or a layer deposition on the SiC surface. Moreover, Si is known to volatilize towards 1400°C at one atmosphere pressure, and in lack of a Si supersaturating vapor the carbonization of the surface is inevitable. This paper presents the results of an optimized thermal rf annealing, which avoids these problems

Study of 6H-SiC high voltage bipolar diodes under reverse biases

International audienceSilicon carbide presents electrical properties suitable for many applications especially for high voltage devices. 6H-SiC P+NN+ structures have been fabricated following ISE software simulations in order to block voltages as high as 1.5 kV. In particular, these diodes are realized by surrounding the emitter by a p-type region called junction termination extension (JTE). Electrical characterizations under reverse bias at, room temperature and in various environments (air, silicone oil) show a premature breakdown for the protected diodes. This breakdown is localized at the emitter periphery. Optical beam induced current (OBIC) measurements show a peak of photocurrent at the junction edge, indicating the presence of a high electric field. These results show a protection efficiency of 60% of the JTE. An electrical activation of the aluminum dopants implanted in the JTE around 30% is derived from the analysis of the presented results

Near breakdown voltage optical beam induced current (OBIC) on 4H-SiC bipolar diode

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Behavior of Space Charge in Polyimide and the Influence on Power Semiconductor Device Reliability

Polyimide is widely used in film form as a passivation material for power semiconductor devices such as Si, SiC, and GaN. The magnitude of the electric field at the edge termination area of these semiconductor devices is becoming higher due to the increase of operational voltage and/or demand for shrinking the edge termination area to increase device active area. Hence, it is concerned that the accumulation of space charge in the encapsulation and passivation material may affect the insulation performance of these devices, for example, the degradation of withstand voltage due to distortion of the internal electric field caused by space charge accumulation. To design space charge resistance of semiconductor devices, it is important to understand the space charge behavior in polyimide films with a thickness of several to several tens of micrometers. This chapter addresses practical implementation, specifications, and issues on space charge in polyimide insulation on power semiconductor devices focusing on the space charge measurements in thin polyimide films using the latest developed LIMM method and DC conductivity measurements

Metallized ceramic substrate with mesa structure for voltage ramp-up of power modules

International audienceAs the available wide bandgap semiconductors continuingly increase their operating voltages, the electrical insulation used in their packaging is increasingly constrained. More precisely the ceramic substrate, used in demanding applications, represents a key multi-functional element is being in charge of the mechanical support of the metallic track that interconnects the semiconductor chips with the rest of the power system, as well as of electrical insulation and of thermal conduction. In this complex assembly, the electric field enhancement at the triple junction between the ceramic, the metallic track borders and the insulating environment is usually a critical point. When the electrical field at the triple point exceeds the critical value allowed by the insulation system, this hampers the device performance and limits the voltage rating for future systems. The solution proposed here is based on the shape modification of the ceramic substrate by creating a mesa structure (plateau) that holds the metallic tracks in the assembly. A numerical simulation approach is used to optimize the structure. After the elaboration of the structures by ultrasonic machining we observed a significant increase (30%) in the partial discharge detection voltages, at 10 pC sensitivity, in a substrate with a mesa structure when comparing to a conventional metallized ceramic substrate