Magnetic cooling for microkelvin nanoelectronics on a cryofree platform

We present a parallel network of 16 demagnetization refrigerators mounted on a cryofree dilution refrigerator aimed to cool nanoelectronic devices to sub-millikelvin temperatures. To measure the refrigerator temperature, the thermal motion of electrons in a Ag wire -- thermalized by a spot-weld to one of the Cu nuclear refrigerators -- is inductively picked-up by a superconducting gradiometer and amplified by a SQUID mounted at 4 K. The noise thermometer as well as other thermometers are used to characterize the performance of the system, finding magnetic field independent heat-leaks of a few nW/mol, cold times of several days below 1 mK, and a lowest temperature of 150 microK of one of the nuclear stages in a final field of 80 mT, close to the intrinsic SQUID noise of about 100 microK. A simple thermal model of the system capturing the nuclear refrigerator, heat leaks, as well as thermal and Korringa links describes the main features very well, including rather high refrigerator efficiencies typically above 80%.Comment: 4 color figures, including supplementary inf

Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1-100) and diameters (i.e., 220-640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (Vth) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep Vth shift (ΔVth) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics