Formation of Silicon Carbide Whiskers from Organic Precursors Via Sol-Gel Method

Silicon Carbide (SiC) was synthesized by carbothermal reduction of silica precursor and carbon precursor. The silica precursor was obtained from tetraethoxysilane. Sucrose was used as carbon source. Tetraethoxysilane (TEOS) was hydrolyzed in acidic water (pH = 2). The molar ratio of TEOS-H2O-EtOH was taken as 1:8:2 in the sol-gel processing. Hydrolysed silica sol was polymerized with sucrose to incorporate carbon precursor into the silica network. The gel thus obtained was dried in an oven at 70 oC and at 100 oC. The solid mass obtained on drying was heat treated at 1000 °C in nitrogen atmosphere to obtain the black glass. It was characterized by FTIR, SEM and TGA. The black glass was further heated to 1500 oC in argon to yield silicon carbide. this resulted in formation of β-SiC whiskers

Separation of Cenospheres from Fly Ashes by Floatation Method

Fly-ashes are non-combustible mineral residues which are produced from coal in thermal power plants. Four different types of fly ashes were collected from different power station in Gujarat. Characterization through SEM shows that fly ash contains cenosphere i.e. gas bubble containing ceramic particle independent of their bulk density. Floatation technique was used for the separation of cenosphere from fly ash. Two solvents with extremely different densities were used for the separation of cenospheres. All methods gave approximately yield of less than 1% cenosphere in fly ash. Color of cenospheres varied from gray to almost white and the value of density range from 0.4 – 0.8 g/cc. Further, chemical composition analysis revealed that cenospheres do not contain any high concentration of hazardous elements

Architectural Support for Optimizing Huge Page Selection Within the OS

© 2023 Copyright held by the owner/author(s). This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ This document is the Accepted version of a Published Work that appeared in final form in 56th ACM/IEEE International Symposium on Microarchitecture (MICRO), Toronto, Canada. To access the final edited and published work see https://doi.org/10.1145/3613424.3614296Irregular, memory-intensive applications often incur high translation lookaside buffer (TLB) miss rates that result in significant address translation overheads. Employing huge pages is an effective way to reduce these overheads, however in real systems the number of available huge pages can be limited when system memory is nearly full and/or fragmented. Thus, huge pages must be used selectively to back application memory. This work demonstrates that choosing memory regions that incur the most TLB misses for huge page promotion best reduces address translation overheads. We call these regions High reUse TLB-sensitive data (HUBs). Unlike prior work which relies on expensive per-page software counters to identify promotion regions, we propose new architectural support to identify these regions dynamically at application runtime. We propose a promotion candidate cache (PCC) that identifies HUB candidates based on hardware page table walks after a lastlevel TLB miss. This small, fixed-size structure tracks huge pagealigned regions (consisting of base pages), ranks them based on observed page table walk frequency, and only keeps the most frequently accessed ones. Evaluated on applications of various memory intensity, our approach successfully identifies application pages incurring the highest address translation overheads. Our approach demonstrates that with the help of a PCC, the OS only needs to promote 4% of the application footprint to achieve more than 75% of the peak achievable performance, yielding 1.19-1.33× speedups over 4KB base pages alone. In real systems where memory is typically fragmented, the PCC outperforms Linux’s page promotion policy by 14% (when 50% of total memory is fragmented) and 16% (when 90% of total memory is fragmented) respectively

Nurses\u27 understanding and management of iron deficiency in Australia: A cross-sectional, exploratory study

Objectives: To assess the experiences and knowledge of nurses in the area of iron deficiency. Design: A cross-sectional, exploratory study using online survey. Setting: Data were collected from nurses working at various primary, secondary and tertiary Australian health practices and organisations. Participants: Australian nurses currently in practice. Method: Australian nurses currently in practice were invited to complete an online survey about their work background, personal experiences with iron deficiency and iron-deficiency identification and treatment. The survey included a nine-item questionnaire to assess knowledge of iron-deficiency risk factors and biochemistry. Results: A total of 534 eligible nurses participated in the survey. Participants were more likely to be female, aged 55-64 years, and working in general practice. Just under half (45.1 %) reported being diagnosed with iron deficiency themselves. Unusual fatigue or tiredness was the most frequent symptom that alerted nurses to potential iron deficiency in patients (reported by 91.9 % of nurses). Nurses who had participated in formal training around iron deficiency in the last 5 years demonstrated a significantly higher knowledge score (4.2 ± 2.1) compared with those who had not or were not sure about their formal training status (3.7 ± 1.9, p = 0.035). Knowledge around the understanding of functional iron deficiency was limited. Conclusions: Nurses report personal experiences of iron deficiency and show good knowledge of symptoms, demonstrating the potential for them to take a leading role in managing iron deficiency in patients. Educational programmes are required to address knowledge gaps and should be offered via various methods to accommodate a diverse nurse cohort. Our research highlights the potential for an expanded scope of practice for nurses in the primary care setting in the area of iron deficiency

Tiny but Mighty: Designing and Realizing Scalable Latency Tolerance for Manycore SoCs

Modern computing systems employ significant heterogeneity and specialization to meet performance targets at manageable power. However, memory latency bottlenecks remain problematic, particularly for sparse neural network and graph analytic applications where indirect memory accesses (IMAs) challenge the memory hierarchy. Decades of prior art have proposed hardware and software mechanisms to mitigate IMA latency, but they fail to analyze real-chip considerations, especially when used in SoCs and manycores. In this paper, we revisit many of these techniques while taking into account manycore integration and verification. We present the first system implementation of latency tolerance hardware that provides significant speedups without requiring any memory hierarchy or processor tile modifications. This is achieved through a Memory Access Parallel-Load Engine (MAPLE), integrated through the Network-on-Chip (NoC) in a scalable manner. Our hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP). In April 2021 we taped out a manycore chip that includes tens of MAPLE instances for efficient data supply. MAPLE demonstrates a full RTL implementation of out-of-core latency-mitigation hardware, with virtual memory support and automated compilation targetting it. This paper evaluates MAPLE integrated with a dual-core FPGA prototype running applications with full SMP Linux, and demonstrates geomean speedups of 2.35× and 2.27× over software-based prefetching and decoupling, respectively. Compared to state-of-the-art hardware, it provides geomean speedups of 1.82× and 1.72× over prefetching and decoupling techniques

miRNA Profiling of Naïve, Effector and Memory CD8 T Cells

microRNAs have recently emerged as master regulators of gene expression during development and cell differentiation. Although profound changes in gene expression also occur during antigen-induced T cell differentiation, the role of miRNAs in the process is not known. We compared the miRNA expression profiles between antigen-specific naïve, effector and memory CD8+ T cells using 3 different methods-small RNA cloning, miRNA microarray analysis and real-time PCR. Although many miRNAs were expressed in all the T cell subsets, the frequency of 7 miRNAs (miR-16, miR-21, miR-142-3p, miR-142-5p, miR-150, miR-15b and let-7f) alone accounted for ∼60% of all miRNAs, and their expression was several fold higher than the other expressed miRNAs. Global downregulation of miRNAs (including 6/7 dominantly expressed miRNAs) was observed in effector T cells compared to naïve cells and the miRNA expression levels tended to come back up in memory T cells. However, a few miRNAs, notably miR-21 were higher in effector and memory T cells compared to naïve T cells. These results suggest that concomitant with profound changes in gene expression, miRNA profile also changes dynamically during T cell differentiation. Sequence analysis of the cloned mature miRNAs revealed an extensive degree of end polymorphism. While 3′end polymorphisms dominated, heterogeneity at both ends, resembling drosha/dicer processing shift was also seen in miR-142, suggesting a possible novel mechanism to generate new miRNA and/or to diversify miRNA target selection. Overall, our results suggest that dynamic changes in the expression of miRNAs may be important for the regulation of gene expression during antigen-induced T cell differentiation. Our study also suggests possible novel mechanisms for miRNA biogenesis and function