2 research outputs found
Optimization of a Solution-Processed SiO<sub>2</sub> Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors
We report on the optimization of
the plasma treatment conditions
for a solution-processed silicon dioxide gate insulator for application
in zinc oxide thin film transistors (TFTs). The SiO<sub>2</sub> layer
was formed by spin coating a perhydropolysilazane (PHPS) precursor.
This thin film was subsequently thermally annealed, followed by exposure
to an oxygen plasma, to form an insulating (leakage current density
of ∼10<sup>−7</sup> A/cm<sup>2</sup>) SiO<sub>2</sub> layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator
for 10 s) possessed a carrier mobility of 3.2 cm<sup>2</sup>/(V s),
an on/off ratio of ∼10<sup>7</sup>, a threshold voltage of
−1.3 V, and a subthreshold swing of 0.2 V/decade. In addition,
long-term exposure (150 min) of the pre-annealed PHPS to the oxygen
plasma enabled the maximum processing temperature to be reduced from
180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility
of 1.3 cm<sup>2</sup>/(V s) and on/off ratio of ∼10<sup>7</sup>
Solution-Processable LaZrO<sub><i>x</i></sub>/SiO<sub>2</sub> Gate Dielectric at Low Temperature of 180 °C for High-Performance Metal Oxide Field-Effect Transistors
Although solution-processable high-k
inorganic dielectrics have
been implemented as a gate insulator for high-performance, low-cost
transition metal oxide field-effect transistors (FETs), the high-temperature
annealing (>300 °C) required to achieve acceptable insulating
properties still limits the facile realization of flexible electronics.
This study reports that the addition of a 2-dimetylamino-1-propanol
(DMAPO) catalyst to a perhydropolysilazane (PHPS) solution enables
a significant reduction of the curing temperature for the resulting
SiO<sub>2</sub> dielectrics to as low as 180 °C. The hydrolysis
and condensation of the as-spun PHPS film under humidity conditions
were enhanced greatly by the presence of DMAPO, even at extremely
low curing temperatures, which allowed a smooth surface (roughness
of 0.31 nm) and acceptable leakage characteristics (1.8 × 10<sup>–6</sup> A/cm<sup>2</sup> at an electric field of 1MV/cm)
of the resulting SiO<sub>2</sub> dielectric films. Although the resulting
indium zinc oxide (IZO) FETs exhibited an apparent high mobility of
261.6 cm<sup>2</sup>/(V s), they suffered from a low on/off current
(<i>I</i><sub>ON/OFF</sub>) ratio and large hysteresis due
to the hygroscopic property of silazane-derived SiO<sub>2</sub> film.
The <i>I</i><sub>ON/OFF</sub> value and hysteresis instability
of IZO FETs was improved by capping the high-k LaZrO<sub><i>x</i></sub> dielectric on a solution-processed SiO<sub>2</sub> film via
sol–gel processing at a low temperature of 180 °C while
maintaining a high mobility of 24.8 cm<sup>2</sup>/(V s). This superior
performance of the IZO FETs with a spin-coated LaZrO<sub><i>x</i></sub>/SiO<sub>2</sub> bilayer gate insulator can be attributed to
the efficient intercalation of the 5s orbital of In<sup>3+</sup> ion
in the IZO channel, the good interface matching of IZO/LaZrO<sub><i>x</i></sub> and the carrier blocking ability of PHPS-derived
SiO<sub>2</sub> dielectric film. Therefore, the solution-processable
LaZrO<sub><i>x</i></sub>/SiO<sub>2</sub> stack can be a
promising candidate as a gate dielectric for low-temperature, high-performance,
and low-cost flexible metal oxide FETs