FERONOC : FLEXIBLE AND EXTENSIBLE ROUTER IMPLEMENTATION FOR DIAGONAL MESH TOPOLOGY

International audienceNetworks on Chip (NoCs) can improve a set of perfor- mances criteria, in complex SoCs, such as scalability, flexibility and adaptability. However, performances of a NoC are closely related to its topology. The diameter and average distance represent an important factor in term of performances and implementation. The proposed diagonal mesh topology is designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). It can contain a large number of nodes without changing the maximum diameter which is equal to 2. In this paper, we present a new router architecture called FeRoNoC (Flexible, extensible Router NoC) and its Register Transfer Level (RTL) hardware implementation for the diagonal mesh topology. The architecture of our NoC is based on a flexible and extensible router which consists of a packet switching technique and deterministic routing algorithm. Effectiveness and performances of the proposed topology have been shown using a virtex5 FPGA implementation. A comparative performances study of the proposed NoC architecture with others topology is performed

Co-design of the H264 application and implantation on a GALS-NoC

L'étude des réseaux sur puces (NoC) est un domaine de recherche qui traite principalement la communication globale dans les systèmes sur puce (SoC). La topologie choisie et l'algorithme de routage jouent un rôle essentiel durant la phase de conception des architectures NoC. La modélisation des structures répétitives telles que les topologies des réseaux sur puce sous des formes graphiques pose un défi particulier. Cet aspect peut être rencontré dans les applications orienté contrôle/données intensif tel que le codeur vidéo H.264. Model Driven Engineering est une méthodologie de développement logiciel où le système complet est modélisé à un niveau d'abstraction élevé en utilisant un langage de modélisation unifié comme l’UML/MARTE. Le profil UML pour la modélisation et l'analyse des systèmes embarqués en temps réel (MARTE) est la norme actuelle pour la modélisation des SoCs.Cette thèse décrit une méthodologie adéquate pour la modélisation des NoCs en utilisant le profil MARTE. L'étude proposée a montré que le paquetage RSM (Repetitive Structure Modeling) du profil MARTE est assez puissant pour modéliser différent types de topologies. En utilisant cette méthodologie, plusieurs aspects tels que l’algorithme de routage sont modélisés en se basant sur les machines d'état. Ceci permet au profil MARTE à être assez complet pour la modélisation d'un grand nombre d’architectures de NoCs. Certains travaux sont en cours pour synthétiser ces réseaux, en VHDL à partir de ces modèles. Pour la validation de la méthodologie proposée, une approche de co-design a été étudiée par l’implémentation d'un système de codage vidéo H.264 sur un NoC de type Diagonal Mesh en utilisant model en « Y » de l’outil Gaspard2. Avant de passer à l'association de l'application/architecture, une optimisation architecturale ciblant la réduction de la puissance consommée du module le plus critique (Estimateur de Mouvement) de l'application a été effectué. Ainsi, une architecture VLSI flexible d’un estimateur de mouvement à blocks variables (FSVBSME) a été proposée.The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role during the design of NoC architectures.The modeling of repetitive structures such as network on chip topologies in graphics forms poses a particular challenge. This aspect may be encountered in intensive data/control oriented applications such as H.264 video coder. Model driven engineering is a software development methodology where the complete system is modeled at a high abstraction level using a modeling language as UML/MARTE. The UML profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) is the current standard for the SoCs modeling. This thesis describes an adequate methodology for modeling NoCs by using the MARTE standard profile. The proposed study has shown that the Repetitive Structure Modeling (RSM) package of MARTE profile is powerful enough for modeling different topologies. By using this methodology, several aspects such as routing algorithm are modeled based finite state machines. This allows to the MARTE profile to be complete enough for modeling a large number of NoCs architectures. Some work is on-going to synthesize such networks in VHDL from such models. While validating the proposed methodology, a co-design approach has been studied by mapping a H264 video coding system onto a Diagonal Mesh NoC by using the Y Chart of Gaspard2 tool. Before allowing the association of the application/architecture, an architectural optimization targeting power minimization of the most critical module of the application has been performed. So, a flexible VLSI architecture for full-search VBSME (FSVBSME) has been proposed

Low power design of wireless endoscopy compression/communication architecture

A wireless endoscopy capsule represents an efficient device interesting on the examination of digestive diseases. Many performance criteria’s (silicon area, dissipated power, image quality, computational time, etc.) need to be deeply studied.In this paper, our interest is the optimization of the indicated criteria. The proposed methodology is based on exploring the advantages of the DCT/DWT transforms by combining them into single architecture. For arithmetic operations, the MCLA technique is used. This architecture integrates also a CABAC entropy coder that supports all binarization schemes. AMBA/I2C architecture is developed for assuring optimized communication.The comparisons of the proposed architecture with the most popular methods explained in related works show efficient results in terms dissipated power, hardware cost, and computation speed. Keywords: Wireless endoscopy capsule, DCT/DWT image compression, CABAC entropy coder, AMBA/I2C multi-bus architectur

A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. At the end of the flow, the implementation code is generated automatically from the high-level models. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering

Co-Design de l'application H264 et implantation sur un NoC-GALS

L'étude des réseaux sur puces (NoC) est un domaine de recherche qui traite principalement la communication globale dans les systèmes sur puce (SoC). La topologie choisie et l'algorithme de routage jouent un rôle essentiel durant la phase de conception des architectures NoC. La modélisation des structures répétitives telles que les topologies des réseaux sur puce sous des formes graphiques pose un défi particulier. Cet aspect peut être rencontré dans les applications orienté contrôle/données intensif tel que le codeur vidéo H.264. Model Driven Engineering est une méthodologie de développement logiciel où le système complet est modélisé à un niveau d'abstraction élevé en utilisant un langage de modélisation unifié comme l UML/MARTE. Le profil UML pour la modélisation et l'analyse des systèmes embarqués en temps réel (MARTE) est la norme actuelle pour la modélisation des SoCs.Cette thèse décrit une méthodologie adéquate pour la modélisation des NoCs en utilisant le profil MARTE. L'étude proposée a montré que le paquetage RSM (Repetitive Structure Modeling) du profil MARTE est assez puissant pour modéliser différent types de topologies. En utilisant cette méthodologie, plusieurs aspects tels que l algorithme de routage sont modélisés en se basant sur les machines d'état. Ceci permet au profil MARTE à être assez complet pour la modélisation d'un grand nombre d architectures de NoCs. Certains travaux sont en cours pour synthétiser ces réseaux, en VHDL à partir de ces modèles. Pour la validation de la méthodologie proposée, une approche de co-design a été étudiée par l implémentation d'un système de codage vidéo H.264 sur un NoC de type Diagonal Mesh en utilisant model en Y de l outil Gaspard2. Avant de passer à l'association de l'application/architecture, une optimisation architecturale ciblant la réduction de la puissance consommée du module le plus critique (Estimateur de Mouvement) de l'application a été effectué. Ainsi, une architecture VLSI flexible d un estimateur de mouvement à blocks variables (FSVBSME) a été proposée.The study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role during the design of NoC architectures.The modeling of repetitive structures such as network on chip topologies in graphics forms poses a particular challenge. This aspect may be encountered in intensive data/control oriented applications such as H.264 video coder. Model driven engineering is a software development methodology where the complete system is modeled at a high abstraction level using a modeling language as UML/MARTE. The UML profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) is the current standard for the SoCs modeling. This thesis describes an adequate methodology for modeling NoCs by using the MARTE standard profile. The proposed study has shown that the Repetitive Structure Modeling (RSM) package of MARTE profile is powerful enough for modeling different topologies. By using this methodology, several aspects such as routing algorithm are modeled based finite state machines. This allows to the MARTE profile to be complete enough for modeling a large number of NoCs architectures. Some work is on-going to synthesize such networks in VHDL from such models. While validating the proposed methodology, a co-design approach has been studied by mapping a H264 video coding system onto a Diagonal Mesh NoC by using the Y Chart of Gaspard2 tool. Before allowing the association of the application/architecture, an architectural optimization targeting power minimization of the most critical module of the application has been performed. So, a flexible VLSI architecture for full-search VBSME (FSVBSME) has been proposed.LILLE1-Bib. Electronique (590099901) / SudocSudocFranceF