3 research outputs found
A Low-Phase-Noise and Area-Efficient Quad-Core VCO Based on Stacked Two-Port Inductors
In this paper, a quad-core oscillator is presented, which exploits a novel stacked two-port inductor topology to couple four oscillator cores. The topology guarantees excellent low-phase-noise performance, while overcoming the drawbacks of multi-core oscillators in terms of power consumption and silicon area occupation. Three different 19.125-GHz quad-core VCOs were designed in a fully depleted silicon on insulator CMOS technology to demonstrate the high design flexibility of the proposed solution that allows power consumption and area occupation to be traded off according to the specific requirements. Although the quad-core VCO design was aimed at 77-GHz automotive radar, the proposed topology can be profitably exploited in RF/mm-wave wireless communication systems
40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber